With the hardware architectures booming over the last decade, the newly-introduced Tensor Core Unit (TCU) on GPU has empowered the process of AI training and inference more efficiently. Although TCU is prevalent and promises a significant increase in performance, they suffer from over-specialization as only matrix multiplication(MM) on small matrices is supported. Due to the diversity of non-MM operations and the limitation of asymmetric MM configuration, previous works only achieved limited success in bridging performance-critical kernels such as stencil computation with FP64 Tensor Cores. They either restrict the stencil parameters, rely solely on low precision, or require extensive changes to the data layout. This paper presents a practical runtime technique, Cladder, for tensorizing traditional Stencil computation to efficiently use versatile TCU while preserving the original accuracy and data layout. Without restricting the stencil parameters, Cladder formulates an efficient mapping of the Stencil computation with a series of tensor operations to leverage the computing power of TCU. To improve the data reuse through the GPU memory hierarchies, a two-level accessing optimization technique, temporal kernel fusion, is proposed innovatively, leading to less data movement and more register saving in a cohesive fashion. Moreover, Cladder identifies the spatial and temporal dependencies carefully, adapts stencils in different shapes to tensors, and paves a generalized way for achieving practical tensorization on Stencil. Experiments demonstrate that Cladder could provide a practical solution for leveraging TCU in Stencil-driven scientific computing and achieve superior performance compared to the related state-of-the-arts.
Achieving high performance for matrix multiplication (GEMM) remains critical in high-performance computing (HPC) and machine learning (ML). As core computational components, micro-kernels determine GEMM efficiency but face challenges in development cost and hardware adaptability—especially on modern General-Purpose DSPs (GPDSPs) with VLIW and SIMD architectures. Existing automatic micro-kernel generation methods on DSP platforms either suffer from suboptimal performance due to general compiler backend limitations or face challenges in handling complex VLIW instruction scheduling and cross-platform adaptability. This paper proposes MAGGIE, an MLIR-based automatic micro-kernel generation approach for GPDSPs that uses a progressive lowering design at two levels: generic optimization (i.e., algorithmic transformations and intermediate code optimization) and backend specialization (i.e., DSP-specific instruction scheduling and memory access fusion). Experimental results on the FT-M7032 DSP platform demonstrate that automatically generated micro-kernels achieve a peak efficiency of 99.2
Dense linear algebra kernels—General Matrix Multiplication (GEMM), Triangular Solve with Multiple Right-Hand Sides (TRSM), and LU decomposition with partial pivoting (GETRF)—serve as foundational computational building blocks for both High-Performance Computing (HPC) and modern Artificial Intelligence (AI). While highly optimized implementations exist for CPUs and GPUs, emerging Neural Processing Units (NPUs) present unique architectural challenges that demand novel algorithmic approaches to achieve peak performance. The Huawei Ascend 910 NPU exemplifies these challenges: each of its 20 AI cores integrates heterogeneous functional units (Cube, Vector, Scalar) capable of concurrent execution. This architecture enables theoretical performance beyond linear core scaling, but only if algorithms can coordinate fine-grained parallelism across these units while addressing complex memory hierarchies. This paper makes following contributions: (1) New Parallelism Discovery Scheduling We identify and formalize previously unexplored parallelism in TRSM and GETRF kernels, then design a provably efficient scheduling strategy to map these opportunities onto the Ascend 910’s heterogeneous units (Cube/Vector/Scalar). This breaks performance limits imposed by core-count scaling. (2) Unified Data Partitioning Strategy We extend traditional communication optimality analyses to the Ascend 910’s intricate cache hierarchy, which features a mix of shared, distributed, inclusive, and exclusive caches. Our unified partitioning strategy achieves asymptotic communication optimality under these complex constraints. Autonomous On-Device Scheduling We develop an autonomous scheduling mechanism that offloads tiling parameter computation entirely to the device, minimizing host-device communication overhead and enabling efficient on-device kernel fusion. Notably, our work establishes the first high-performance algorithmic baseline for TRSM and GETRF on the Ascend NPU platform, addressing a critical gap in the existing ecosystem. To validate our approach, we implement the kernels integrated with these techniques on the Ascend 910 NPU, achieving consistent speedups of 2-3 × over the highly optimized NVIDIA A100 cuBLAS/cuSolver library and MAGMA. Remarkably, this performance is achieved despite the Ascend 910’s comparable theoretical FLOPS and lower memory bandwidth relative to the A100. These results demonstrate that algorithmic innovation can unlock the full potential of NPUs, enabling them to outperform state-of-the-art GPUs in dense linear algebra tasks, even without superior raw hardware specifications. This work significantly broadens the applicability of NPUs for HPC and AI workloads, challenging the notion that performance is inherently tied to core count or peak hardware capabilities.
The Yin-He Global Spectral Model (YHGSM) is one of the most representative numerical weather prediction (NWP) models in China and has already been operationally applied to global weather forecasting. At present, YHGSM has achieved satisfactory parallel performance on high-performance computing (HPC) platforms to meet the real-time requirements of operational forecasting. However, when using the parallel two-dimensional (2D) domain decomposition algorithm, communication overhead still significantly impacts the overall performance of YHGSM. To address this issue, we introduce a pipelined optimization scheme in the Inverse Legendre Transform stage, aiming to reduce communication overhead through computation–communication overlap. Specifically, computation and communication tasks are grouped along the vertical dimension, where data dependencies are relatively weak, enabling the communication of one group to be overlapped with the computation of another. Experiments conducted on HPC platforms demonstrate the effectiveness of this approach and highlight its potential for broader application in spectral models. Under the best-case configuration, the proposed optimization reduces communication time by up to 75
The integration of Single Instruction, Multiple Data (SIMD) extensions has become crucial for enhancing computational performance. While loop-level and superword-level vectorization techniques have matured, function-level vectorization remains challenging. Existing OpenMP declare simd mechanisms require repetitive annotations at both function declarations and call sites–particularly cumbersome across separate compilation units–thus limiting their practical applicability. This paper presents Automatic Function-level Vectorization (AFV), a directive-based framework designed to simplify function-level vectorization within OpenMP. We propose managing function vectorization directives at the loop level rather than the function level, thereby extending the OpenMP API with AFV directives. Additionally, we introduce an optimization framework at the intermediate representation stage that automatically inserts vectorization directives into called functions, generating vectorized versions and enhancing loop vectorization that includes function calls. Importantly, this approach remains effective for function calls across compilation units. Experimental evaluation using benchmarks from Intel’s SPMD Program Compiler and SIMD libraries validates the framework’s superiority across four dimensions: in terms of performance, AFV achieves 1.65 × higher performance than OpenMP; in instruction optimization, it reduces instruction count by 12.38
Due to unprecedented performance, large-scale language models (LLMs) have become widespread in various fields. Researchers have developed many heuristic parallelism strategies to facilitate training in high-performance computing platforms as LLMs grow too large to be trained on a single node. However, distributed deep learning performance models suffer from inaccurate and time-consuming problems to help determine optimal strategies. To solve this, we propose ParallelSim, an accurate, generic, and efficient simulator designed to estimate the performance of various strategies. ParallelSim can simulate distributed deep-learning programs written in PyTorch by converting the models into intermediate representation sub-graphs. To enhance ParallelSim’s accuracy, we analyze profiling errors and overlap from the perspective of GPU hardware design, adapting the profiling logic to more accurately model real-world scenarios. ParallelSim uses a hierarchical simulation engine that decouples the execution of inter-stage and intra-stage to accelerate the simulation. Finally, we evaluate ParallelSim on 16 DGX A100 nodes. The experimental results show that ParallelSim has an average prediction error of 1.83
Large-scale scientific simulations increasingly adopt statistical distribution representation for lightweight data storage and analysis. We propose a method for selecting key time-steps of time-varying scientific data based on parametric-distribution models. Our solution establishes a similarity measurement method for complex distribution models of scientific datasets. The distribution similarity serves as the criterion for the hierarchical clustering to generate a set of short and continuous time intervals. We then iteratively merge these time intervals according to the deviation vector representation of the distribution model. The deviation vector is used as termination iteration conditions to obtain the final time intervals from which representative time steps can be selected. Our solution can achieve automated selection without explicitly feature defining or labeling, while significantly reducing computational overhead with comparable quality. We demonstrate the effectiveness of our approach based on the distribution space through five different real-world scientific applications.
We have optimized the parallel threshold ILU algorithm (ParILUT) for GPUs. The optimizations are for three building blocks: candidate search and ILU residual computation, adding and removing elements, and threshold selection. Firstly, we fuse candidate search and ILU residual computation by modifying the ParILUT algorithm and extending the register-aware SpGEMM algorithm to calculate it. At the same time, we developed a GPU bin search algorithm to make the register-aware SpGEMM algorithm perform better in ParILUT. Secondly, we adopt a warp-row-parallel approach to add elements to new L and U and remove elements from candidates instead of the thread-row-parallel approach. And used the efficient GPU instructions to locate the positions of elements. Thirdly, we proposed a balanced classification tree in the threshold selection to balance the buckets’ data, when a large number of elements with the same value. Finally,we experimented with the performance of each optimization and the whole ParILUT. And verified the correctness of the optimized ParILUT. The result indicates that the optimized ParILUT average speedup is 4.03 times over the original version, and the speedup increases with the amount of fill-in.
High-performance computing (HPC) systems must remain stable and reliable to consistently deliver robust computational power and ensure the proper execution of user jobs. Anomaly detection is a key means to ensure the stability and reliability of these systems. With the expansion of HPC systems and changes in their architecture, accurately identifying anomalies in dynamic environments has become increasingly challenging. Traditional detection methods rely on experience and rules, which could be inefficient and inaccurate. To address these issues, researchers have proposed machine learning-based methods to automatically process large amounts of complex data, improving the efficiency of anomaly identification and diagnosis. In this survey, we conduct a comprehensive and in-depth investigation of machine learning-based anomaly detection methods in HPC systems. Firstly, we summarize and introduce the background and challenges of anomaly detection in HPC systems. Secondly, we compare a series of machine learning-based anomaly detection works in detail and summarize their frameworks. We conclude their advantages and disadvantages and application scenarios. Finally, we discuss several promising development trends of machine learning-based HPC system anomaly detection.
With the increasing number of computationally intensive applications, heterogeneous systems have become an important solution for improving computing performance. In order to effectively develop and optimize parallel programs running on these systems, performance prediction has become an indispensable part. This article aims to comprehensively review the methods and tools for predicting parallel program performance in heterogeneous systems, analyze the characteristics of existing technologies, explore their development trends, and provide valuable references and guidance for researchers and developers. This article adopts a systematic review method, first sorting out the research process of parallel program performance prediction in heterogeneous systems, and then classifying and summarizing the current mainstream performance prediction methods, including analysis model-based prediction, simulation-based prediction, and machine learning based prediction. This article also summarizes the tools and platforms used to predict parallel program performance in heterogeneous systems. Through review, it was found that various performance prediction methods and tools have their own advantages in feature richness, availability, and accuracy, but they have all improved the efficiency and accuracy of parallel program performance prediction to a certain extent. The review of this article indicates that despite various methods and tools available for performance prediction, there are still many challenges and unresolved issues. Future research should further explore more accurate, efficient and intelligent prediction methods to better support the development and optimization of parallel programs in heterogeneous systems.
This survey has provided a systematic overview of the emerging field of LLM-enabled compilation by addressing several key research questions. We first answered how LLMs are being integrated by proposing a comprehensive, multi-dimensional taxonomy that categorizes works based on their Design Philosophy (Selector, Translator, Generator), LLM Methodology, their operational Level of Code Abstraction, and the specific Task Type they address. In answering what advancements these approaches offer, we identified three primary benefits: the democratization of compiler development, the discovery of novel optimization strategies, and the broadening of the compiler's traditional scope. Finally, in addressing the field's challenges and opportunities, we highlighted the critical hurdles of ensuring correctness and achieving scalability, while identifying the development of hybrid systems as the most promising path forward. By providing these answers, this survey serves as a foundational roadmap for researchers and practitioners, charting the course for a new generation of LLM-powered, intelligent, adaptive and synergistic compilation tools.
Large language models (LLMs) have the potential to revolutionize how we design and implement compilers and code translation tools. However, existing LLMs struggle to handle long and complex programs. We introduce LEGO-Compiler, a novel neural compilation system that leverages LLMs to translate high-level languages into assembly code. Our approach centers on three key innovations: LEGO translation, which decomposes the input program into manageable blocks; breaking down the complex compilation process into smaller, simpler verifiable steps by organizing it as a verifiable LLM workflow by external tests; and a feedback mechanism for self-correction. Supported by formal proofs of translation composability, LEGO-Compiler demonstrates high accuracy on multiple datasets, including over 99
The Least Mean Square (LMS) adaptive filtering algorithm is a significant filtering algorithm widely used in noise processing and other fields that automatically adjusts the values of filter coefficients according to the results, aimed at optimizing the filtered results. Based on a basic serial LMS adaptive filtering algorithm, we propose a vectorized parallel processing scheme for the LMS adaptive filtering algorithm in this work. By combining the characteristics of the algorithm processing flow and those of the parallel technologies used in vector Digital Signal Processes (DSPs), the optimizations such as loop fusion, double-word accessing, and vector shuffling of the LMS algorithm are studied in depth, and the loop unrolling optimization method is used to accelerate the calculation of the algorithm further. Experimental research was conducted on the high-performance FT-M7002 DSP platform in this paper. The results show that, compared with the running performance of the LMS adaptive filtering algorithm in Texas Instruments (TI)’s dsplib library on the TMS320C6678 processor, the optimization effect of the proposed optimization algorithm in this paper can achieve a maximum speed-up ratio of up to 6.9 × for medium-scale data. The merged memory access optimization implemented on the GPU platform achieves an average 1.5x speedup compared to the basic parallel scheme.
As high performance computing (HPC) moves towards exascale, storage systems face core challenges such as data flooding, bandwidth bottlenecks, mixed load coordination, and performance cost balancing. This article systematically reviews the cutting-edge technologies of high performance storage systems, covering four aspects: storage architecture, hardware, software, and networking. At the architecture level, storage computing separation, distributed and hierarchical architectures decouple computing and storage resources, and optimize latency and scalability through high-speed networks. Typical cases include supercomputer systems such as Frontier and Fugaku. In terms of hardware, persistent memory, all flash array, and integrated storage and computing chips significantly improve throughput and reduce latency, while ZNS SSD and QLC technology optimize cost and lifespan. At the software level, distributed parallel file systems respond to massive small files and high concurrency access through burst buffering technology. In network communication, low latency protocols such as Slingshot, InfiniBand, and RoCE support TB level bandwidth, while CXL technology promotes storage resource pooling. In the future, photon interconnection, AI native architecture, and green energy-saving technologies will further promote the development of high performance storage towards efficiency and intelligence, to support ZB level storage requirements in scenarios such as Exascale computing and AI training.
In modern warfare, decoy targets are often set up by the enemy to interfere with the combat of unmanned aerial vehicle (UAV) swarms. To enhance the combat effectiveness of UAV swarm collaborative target assignment and improve its anti-interference ability, we model this problem as a deletion-robust submodular maximization problem with a knapsack constraint. We provide a two-stage framework consisting of a preprocessing algorithm and postprocessing algorithms. Simulation experiments are carried out through the weapon allocation problem and the UAV swarm collaborative target assignment problem. The results show that the proposed algorithms perform better than non-deletion-robust algorithms in terms of objective function values and running time, verifying the effectiveness of the algorithms.
In cloud-edge collaboration systems, real-time data generated by massive heterogeneous terminal devices, such as smart sensors, industrial controllers, and wearable devices, needs to be processed with low latency through distributed servers. However, the heterogeneity of servers, such as differences in computing power, storage, and dedicated acceleration chips, and placement constraints, such as location-sensitive devices only being able to access specific servers, make the multi-resource allocation problem highly complex. At the same time, as an external resource independent of the server, the limited bandwidth of wireless channels needs to be shared by all devices in competition, further exacerbating the difficulty of ensuring fairness. The existing multi-resource allocation mechanism does not consider the placement constraints of servers and the collaborative scheduling of communication computing resources. In addition, in cloud-edge collaboration systems, “least picky users", which can access all edge servers, coexist with “picky users", which can only access some nodes, and a new mechanism needs to be designed to avoid excessive resource allocation bias towards devices with limited access capabilities. This article proposes a multi-resource allocation mechanism based on any price share (APS) (Babaioff et al. in Math Oper Res 49(4):2180–2211, 2023), called APSF, which achieves fair allocation of computing, storage, and communication resources in cloud-edge collaborative systems with placement constraints and an external resource. Through theoretical proof and large-scale simulation verification, the APSF mechanism significantly improves performance while ensuring important properties such as Pareto optimality, sharing incentive, strategy-proofness, local envy-freeness, and bottleneck fairness.
Many sequence mapping tools for next-generation sequencing (NGS) have emerged over the past decades, but most are inefficient in mapping large-scale sequencing NGS data on high-performance servers. This paper proposes a novel and ultra-fast mapping algorithm, ScalableAligner (SA), designed for mapping short reads on multi-core servers. We optimize map-ping logic by combining Divide Conquer strategy, BWT-FM index, and auxiliary hash table to accelerate mapping while keeping mapping precision. We optimize software implementation with lock-free queues, lock-free thread pools, reclaimed memory blocks, separate read–write threads, and asynchronous IO to improve thread, memory, and IO bandwidth utilization. Comparative experiments with Kart, Bowtie2, Hisat2, BWA-MEM2, and Accel-Align show that SA achieves the fastest mapping speed while maintaining high sensitivity and accuracy on multiple datasets, with a speed improvement of 22–50 https://github.com/langbi25/ScalableAligner.git .
Prompt learning has become crucial for adapting Visual Language Models (VLM) to downstream tasks. Although existing prompt learning models have made significant strides, they still face two major challenges: 1. Too much attention is paid to learning about basic classes, making it harder to understand novel classes; 2. Most methods only rely on the context information provided by the prompt template, resulting in limited text features. In this study, we propose a new fine-tuning method for Visual-Language Models called Input-Enhanced Prompt Tuning (IEPT). The IEPT improves the generalization of VLMs for downstream tasks by introducing two components, i.e., the Data Augmentation Framework (DAF) and the Category Generalization Optimizer (CGO). Specifically, the DAF employs Large Language Models to resolve issues of word ambiguity by obtaining more class label context, and uses simple image augmentation to address the issue of limited features by providing more image samples. The CGO prevents overfitting by adding new class names during training. Experiments show that the performance of IEPT in various evaluation suites is better or comparable to that of the existing method, covering basic to novel generalization, domain generalization, and cross-dataset evaluation. Compared to the state-of-the-art method PromptSRC, IEPT achieves an absolute improvement of 0.40 https://github.com/ayuan0626/IEPT .
In this paper, we consider the online parallel-machine customer order scheduling with delivery time and penalties. Given a set of customer orders 𝒪 and a set of dedicated machines ℳ , each customer order consists of m different types of products, and each dedicated machine can only process one type of products. Each customer order can either be accepted and processed by the dedicated machines or rejected and paid a penalty. If a customer order is processed, an additional delivery time is required after processing, so the delivery completion time of a customer order is the sum of its processing completion time and delivery time. In the online setting, customer orders arrive one by one. When a customer order arrives, we must immediately and irrevocably determine whether to process or reject this customer order without any information about the following customer orders. This problem is to schedule an accepted set A and a rejected set R to minimize the sum of the maximum delivery completion time and the penalty cost for rejected customer orders. We present an online algorithm with a competitive ratio of m + 2 , where m is the number of machines in ℳ .
