Digital Twins exhibit heterogeneous spatial accuracy requirements across simulation domains. Spatial error–driven Level of Detail schemes exist for rasterization but are not directly applicable to Bounding Volume Hierarchy–traversal algorithms, such as ray tracing or collision detection. This work introduces a unified detail hierarchy that supports both algorithmic paradigms. We integrate clustered triangle mesh representations (meshlets) with multi-attribute mesh simplification while tracking approximation error per cluster. We present a specialized Quadric Error Metric that accurately captures the spatial error required for Digital Twin simulations. Additionally, we propose a unified clustering method that balances the spatial requirements for low Surface Area Heuristic in Bounding Volume Hierarchy traversal with the topological and fullness constraints necessary for rasterization, enabling a single cluster representation. We further introduce a method to integrate clusters from all Levels of Detail with spatial error into a single Bounding Volume Hierarchy by alternating construction priorities between spatial error and Surface Area Heuristic at consecutive levels. This mitigates excessive overlap from stacked clusters and improves pruning during traversal. The method is highly parallelizable and exhibits scalability on both CPUs and GPUs. Experiments demonstrate substantial geometry pruning within spatial error thresholds, yielding significant computational savings while maintaining accuracy requirements.
This article introduces parallALT—a fully spectral spherical harmonic transform library. Developed for modern massively parallel accelerators, such as GPUs, parallALT combines close to machine-precision accuracy with exceptional performance. This article demonstrates that our fully spectral algorithm has \(O(\sqrt {L})\) (with L being the spherical harmonic degree) round trip accuracy scaling compared to O(L) scaling of the conventional quadrature approach. We also show that parallALT implementation for high L ∈ [512, 16384] is up to three times faster on an Nvidia H100 GPU than the most efficient open source quadrature implementation, SHTns. Developed with the help of the in-house cross-platform runtime code generation platform, PfSolve and VkFFT libraries, parallALT will be released as an open source library in the future.
This article presents a high performance fully in-GPU inductive logic learning algorithm. The proposed algorithm performs all inductive logic learning activities such as hypothesis search and hypothesis evaluation, fully in-GPU with zero CPU involvement. The core contribution of this work, is a high performance fully in-GPU ILP (inductive logic programming) algorithm in description logic (DL), that also supports parallel hypothesis search. The proposed learner addresses the ILP research gap of non-existing GPU-based parallel hypothesis search approaches that target more expressive logics like FOL (first order logic) and DL. Within the proposed learner, we also propose a set of high performance GPU-based hypothesis evaluation algorithms. In addition, the proposed learner is based on the DL-Learner[ 11 ] (the state-of-the-art in DL-based ILPs), with which the proposed learner incorporates many of the DL-Learner’s search strategies – like deterministic ordering of hypotheses operands, to reduce the size of the search space. According to experimental results on four datasets, the proposed in-GPU learner is always faster than the DL-Learner on all datasets; for example, in the IMDB dataset, the proposed learner is faster by up to ~ 18 folds than the DL-Learner (represented using SPILDL at BeamWidth = 1). When considering the average of all hypothesis search beam widths, the proposed learner is always faster than SPILDL[ 6 ] on all datasets; SPILDL is our high performance CPU-based parallel learner in DL. In the Dunnhumby Retail dataset, on average, the proposed learner is faster than SPILDL by ~ 6.55 folds. In terms of worst case scenario, it is demonstrated through parallel search at certain beam width values. For example, at BeamWidth = 8 in the trains dataset, SPILDL is faster than the proposed learner by ~ 2.4 folds.
Deep neural networks (DNNs) have become foundational to modern applications, yet their substantial computational and memory demands pose major obstacles to energy-efficient inference. Moreover, the rapidly expanding parameter footprint and structural diversity further amplify data movement, leading to substantial energy consumption and latency overheads. To address these issues, we propose a novel accelerator, S-TRAC , that dynamically adjusts sparsity t h r esholds through a lgorithm-hardware c o-design to enable efficient DNN inference. At the algorithm level, we employ a static sparse-dense storage format and a dynamic bit-processing scheme to skip non-contributing bits without sacrificing weight precision. At the hardware level, we introduce a column-wise processing-element array with LUT-based shift-accumulate multiplication and a global partial-sum accumulator to sustain energy-efficient execution. To support the proposed algorithm-hardware co-design, we propose a RISC-V extension that coordinates the read, arrangement, multiplication, accumulation, and write stages to support end-to-end accelerator execution. Experimental results show that S-TRAC increases effective sparsity by an average factor of 8.4 × across the evaluated DNN models, enabling substantial memory savings. S-TRAC design achieves 11.16 × energy efficiency and 37.03 × hardware efficiency improvements over state-of-the-art solutions.
In this study, approaches to the development of interactive Java algorithms intended for dynamic visualization of parallel computational threads were considered. The proposed interactive Java algorithms give an opportunity to create visual graphical representations of parallel processes, their interactions, and data distribution. Within the framework of the research the key approaches to visualization of parallel computational flows are analyzed, the peculiarities of the applied interactive components are estimated and the methods of integration with existing monitoring and debugging systems are considered. With the help of configurable visualization tools, developers and researchers can observe the evolution of computational threads, evaluate the performance of systems and timely react to changes in the structure of parallel tasks. Implementing algorithms on the Java platform ensures portability, broad applicability, and integration with existing frameworks for high-performance computing. The use of dynamic data structures, thread-safe collections and parallelism mechanisms implemented in the language and standard libraries allows efficiently processing large amounts of data in real time. In addition, Java Virtual Machine provides profiling tools that can be directly applied to optimize the visualized processes.
