A reference noise rejected current mirror with a fast start-up mechanism is proposed in this paper. A very low frequency pole, which is 7.2-kHz in this design, can be implemented at the bias circuit so that noise coming from bias generating circuits can be heavily filtered. A fast start-up mechanism by moving that 7.2-kHz pole to a much higher frequency is also proposed to speed up its turn-on process. This fast start-up mechanism reduces the start-up time from more than 100-mu s to 0.2-mu s, and it consumes no steady current after start-up. Simulations show that the proposed circuit can reject the reference noise significantly, ease the noise design of the reference generating circuit, consume no DC current in operation, achieve a fast start-up, and occupy a small chip area.
The Bus Switch mechanism is a recently proposed bus encoding technique for low-power off-chip data buses. The approach is based on clustering, reordering and encoding the bus input lines according to a reordering pattern and a fixed coding function. This work presents a statistical approach for reducing the hardware overhead of the bus switch technique, by operating with a sub-set of the possible reordering patterns. We demonstrate the effectiveness and robustness of the proposed approach by ANSI C simulations, measuring the average switching activity savings. Our results show a modest switching activity degradation while saving 90% computation time, thus obtaining a sub-optimal encoder configuration satisfactory for a large variety of benchmarks.
In this paper, we study and analyze the computational complexity of H.264/AVC baseline profile decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, the operations of content activity check, and the edge filtering are known to be very time consuming in the embedded system. In order to reduce the memory reference and improve overall system performance, we proposed a new efficient VLSI architecture to accelerate the processing of deblocking filter. The proposed architecture is called “Adaptive Edge Filtering Operation (AEFO),” which could be embedded in a platform-based architecture as a co-processor. As a result, the performance of the embedded system using AEFO is 1.66 times faster than software implementation. Moreover, the number of total me mory references for loading and storage is reduced by 34% and 36% respectively.
A simple method for the design of FIR filters is presented. It is based on small tables of transition-band samples we optimized for various passband/stopband ripple ratios. The required table, corresponding transition samples and filter order can be selected from the desired passband/stopband ripple, attenuation and transition bandwidth. The samples in the frequency domain can be used for recursive filter realization which consists of comb filter cascaded with a bank of resonators. Such realization in some applications may be considerably more efficient than convolution. Proposed design is simple and fast with sufficient accuracy, as by window method. It offers, however, better attenuations, because the transition samples are optimized here for various passband/stopband ripple ratios.
A low power current-mode analog to digital converter suitable for equipment are required low voltage, low power (ADC). It uses a quartzite level with current injection technique to increase the speed of current mirrors. And this method to reduce the required input signal for a given range and higher operating speeds.In this paper, the feasibility of current-mode algorithmic ADC is demonstrated and advantages of various 2 techniques for use in the converters are considered. Experimental results for 4-bits algorithmic ADC using a 0.8 mu m CMOS technology are reported, including power consumption.
