In many aspects of microprocessor systems design and diagnosis, temporal reasoning of a sequence of event changes occurring at imprecisely known time instants is often required. By combining the change-based and time-based approaches of temporal logics, the concept of time range is proposed as a key component of an enhanced time structure which captures the notion of time impreciseness in event occurrence. A practical MC68000 CPU-memory interface design problem is used as an extensive example to illustrate the various temporal reasoning techniques derived from this new time structure. Efficient methods for time referencing, constraint satisfaction and propagation of time ranges have been developed for embedding domain knowledge in a deep-level constraint model. It is also shown how different shallow rules (regarded as expert's rule of thumb) for system diagnosis can be generated and explained through an inference process of the constraint model.
A minimisation method for Reed-Muller polynomials in mixed polarity known as the decomposition method is developed. The method adopts the top-down approach in which the products of a Reed-Muller polynomial are decomposed from a 1-term list one by one. It can be implemented on computers. Tristate maps can also be used if the number of variables is equal to, or less than, six.
A technique for eliminating hard-to-test or untestable nodes in CMOS integrated circuits is presented. The technique is characterised by a speed degradation smaller than that introduced by others. Also, efficient methods for inserting and condensing test points in combinational circuits are introduced. The experimental results show that only few test points are needed to dramatically reduce the number of random patterns which are required to achieve very close to 100% fault coverage.
The paper describes the underlying theory and an outline for an algorithm which is designed to utilise the power of SIMD computers to detect and locate the presence of logic hazards in combinational logic circuits.
In the paper we make a comparative study of two techniques to design error-detectable array architectures. These techniques are the redundant binary representation (RBR) where the data is encoded in the 1-out-of-3 code; and the two-rail logic where the data is encoded in the 1-out-of-2 code. In recent work, the RBR has been used to achieve online error detection and localisation by checking the data on the array borders. Here we show that another approach is also possible, with less hardware cost, where the checking takes place on the local (processor) level. This provides immediate error detection without delay. The performance of the RBR approaches has been compared with the two-rail approach. The results show that the RBR approaches require more hardware overheads, for small word lengths (n). However, the hardware cost of the two techniques are approximately the same for large n, while the RBR approaches offer much faster arithmetics for all n.
