The Electrocardiogram (ECG) is a graphical representation of the electrical activity of the heart that is captured through a non-invasive process and is used to monitor the state of the heart. Because of its low power, ECG signal is often contaminated with different types of noises. Noisy ECG recording often leads to misinterpretation of heart disease. Hence, denoising of ECG signal is utmost important for accurate assessment of heart health. Addressing this issue, the paper presents a real-time composite digital filter model that attenuates noise from a corrupted ECG signal. The proposed model integrates three classical digital filters: an elliptic high pass infinite impulse response (IIR) filter, moving average (MA) type finite impulse response (FIR) low pass filter, and IIR elliptic band stop filter. All filters are realized using transposed structure and implemented on FPGA platform. The soft model is developed through graphical programing in MATLAB Simulink by using only basic Xilinx System Generator (XSG) blocks and is emulated in Zedboard Zynq-7000 FPGA board. For hardware emulation of the model, 2.61% of total available resource is utilized and 0.278 W on-chip power is consumed. The Worst Negative Slack (WNS) for our design is 2.789 ns, indicating that it meets all required time constraints and the hardware implementation of the soft design is successful on the FPGA board. The model is tested using 376 ECG recordings from the MIT-BIH Normal Sinus Rhythm, MIT-BIH Arrhythmia, and ECG-ID databases. Additionally, we have introduced various noise signals from the MIT-BIH Noise Stress Test database and synthetically generated in MATLAB to further corrupt the ECG signals. The average improvement in signal-to-noise ratio (SNRimp) achieved by our model is 7.61 dB for the ECG-ID database, 6.9 dB for the MIT-BIH Arrhythmia database, and 8.42 dB for the MIT-BIH Normal Sinus Rhythm database. The average root mean square error (RMSE) values are 0.0975, 0.2616, and 0.2168, and the average percentage root mean square difference (%PRD) values are 77.91, 64.11, and 68.21 are computed, respectively.
We investigated osmotic energy generation in a bioinspired nanochannel with grafted polyelectrolyte layer (PEL) by varying the porosity of the PEL. Using finite element based numerical solver, we solved the governing transport equations numerically. In the limiting scenario, we validated our numerical model using theoretical result. We thoroughly studied the cationic concentration field, axial electric field, cationic and anionic current, transference number, net current, diffused potential, maximum power density, and maximum energy conversion efficiency by altering the PEL porosity and the concentration of salt in the left-side reservoir. Together with the changes in reservoir concentration, we found that the PEL porosity significantly influences the axial electric field intensity and cationic concentration field. For the reservoir concentration below the critical limit, it was found that the power density increases with PEL porosity. The highest energy conversion efficiency, on the other hand, was shown to be decreasing as the polyelectrolyte’s porosity increased. The findings of this study contribute to a better understanding of the effects of polyelectrolyte porosity on osmotic energy generation and may aid in the design of high-power density renewable energy generation devices.
This article presents a novel hybrid coupled-inductor (CI) cascaded high step-up (HCICHSU) DC-DC converter tailored for renewable energy systems. The proposed converter achieves ultrahigh voltage gain, low voltage stress on semiconductor devices, and continuous input current by combining buck-boost and boost topologies within a hybrid cascaded structure. The topology targets large conversion at a moderate duty cycle while keeping device stresses low and maintaining a smooth input current. Continuous-conduction operation is analyzed, and expressions for voltage gain, device stresses, and component sizing are derived. A loss model and sensitivity discussion identify dominant loss mechanisms at high conversion ratios. For control, a small-signal model is developed, and the inherent right-half-plane zero (RHPZ) is handled using a Type-III compensator. Experimental verification uses a 160 W prototype stepping 24 to 200 V. The converter reaches 94.4% efficiency at full load and limits drain-to-source peak voltages to about 48 and 60 V for the two main switches, confirming effective leakage-energy recovery and stress reduction in practice. Measured waveforms show stable regulation and consistent currents.
This work focuses on designing a winner-take-all (WTA) algorithm using digital circuits, rather than the more commonly used analog circuits. In this context, neurons are represented as digital bits, similar to those in convolutional neural networks (CNNs) and weightless neural networks (WNNs). The proposed WTA circuit compares the most significant bits (MSBs) of all neurons (or discriminators) in parallel. The results of this initial comparison are then used to evaluate the second MSBs, where a parallel comparison is performed. This process continues iteratively for each subsequent bit until the least significant bits (LSBs) are analyzed. By removing less significant neurons early in the process, the number of signals that switch activity in subsequent comparisons is decreased, thereby reducing overall dynamic power. The WTA circuit consists of an array of OR-AND configurations that employ low-cost CMOS logic gates and operate without a clock or any form of synchronization. This design inherits the advantages of scalability and configurability: adding a new neuron requires only inserting a new row of cells, while increasing the size of the neurons can be accomplished by adding new columns of cells. The design characteristics rely on two factors: the number of neurons (K) and the size of each neuron (N bits). Neuron size plays a crucial role in determining the critical path delay.
This paper introduces a novel image-denoising technique that integrates a hybrid deep learning (DL) model with a self-improved orca predation (SOP) strategy. This hybrid model improves denoising performance by integrating a Convolutional Neural Network (CNN) with Bidirectional Long Short-Term Memory (Bi-LSTM). The hybrid model’s hyperparameters are enhanced using the SOP technique, resulting in superior denoising outcomes. The proposed approach is experimentally tested with the INbreast and CBIS-DDSM datasets. The results demonstrate that the suggested method outperforms conventional approaches, making it a viable option for image-denoising applications. The suggested technique achieved a PSNR of 35.905 on the INbreast dataset and 37.08 on the CBIS-DDSM dataset. However, the DL model demands a significant amount of memory and computing capacity, limiting its implementation on edge devices and causing computing delays and energy loss. Field Programmable Gate Arrays (FPGAs) are ideal for practical applications due to their high computational capability and low power consumption. In this paper, we implement the proposed model on a ZCU104 FPGA board, evaluate its performance, and analyze resource utilization. The experimental outcome shows that the proposed network on the chosen FPGA achieves an impressive execution time of 4.25 s, low power consumption of 3.2 W, and a throughput of 47 images per second.
