Photovoltaic (PV) integration into the power grid is promptly progressing, propelled by continuous improvements in power electronics and Maximum Power Point Tracking (MPPT) strategies. An improved grid-connected PV system is introduced in this paper, integrating an Interleaved Triple Gain Ultra Boost Converter (ITGUBC) to enhance voltage gain and suppress ripple. It features a single-switch structure and employs three winding Coupled Inductor (CI) architecture. A Zebra Optimised Adaptive Incremental Conductance (ZOA-INC) MPPT algorithm is incorporated to optimise PV energy extraction. The proposed MPPT algorithm aims to achieve rapid adaptation, fast response, lower steady-state oscillations and high tracking efficiency. A bidirectional DC-DC converter is integrated with a Battery Energy Storage System (BESS) for power balancing and grid stability. The three-phase Voltage Source Inverter (VSI), regulated by a Proportional-Integral (PI) controller, which guarantees smooth and effective power feeding into the grid while maintaining low Total Harmonic Distortion (THD). Through extensive MATLAB simulations and hardware testing, the system is shown to sustain a stable DC-link voltage, deliver high power efficiency (98.92%) and enhance grid synchronisation. Comparative analysis with traditional MPPT techniques highlights the superior adaptability and tracking accuracy of the proposed method in dynamic scenarios.
Electric vehicles (EVs), in practical use, need motor-control methods that can give quick speed response, low torque ripple, and better energy use under changing road, load, and battery conditions. Permanent Magnet Synchronous Motors (PMSMs) are commonly preferred for EV traction due to their high torque density, compact design, and good efficiency, though their performance may reduce under nonlinear dynamics, disturbances, parameter variation, and State-of-Charge (SOC) changes. This paper proposes a hybrid nonlinear SMC supported by Dynamic Harris Hawks Optimisation (D-HHO). D-HHO acts as a supervisory tuner and updates SMC gains during simulation using recent speed error, motor response, and control effort. A lightweight predictive layer adjusts the boundary before expected speed changes, while an SOC-aware loop moderates control action to reduce unnecessary battery use. The controller is evaluated in MATLAB/Simulink using a UDDS-based EV speed profile and representative PMSM operating points. Compared with PID and fixed-gain SMC, the proposed method improves speed tracking, torque smoothness, current distortion, torque ripple, and energy utilisation.
In this article, a comparison study of Si FinFET and GaAs FinFET is performed, with special attention paid to the changes that occur in their parameters depending on the temperature variation. Various parameters, including switching efficiency, threshold voltage, transconductance, capacitance and frequency responses, are analysed thoroughly. The study shows that the GaAs FinFET device demonstrates higher switching efficiency, lower leakage current, and better frequency response than the Si FinFET. Furthermore, the paper explores how temperature affects some other important device performances like drain current, threshold voltage, DIBL, transconductance, gate capacitance, cut-off frequency and the product of transconductance and frequency. Moreover, an analysis of the effects of varying temperatures between 275K and 350K on some other performances related to linearity is carried out. These analyses include third-order intercept phenomena, harmonics, voltage intercepts, intermodulation distortion, and compression characteristics. All the simulations have been performed using the Silvaco ATLAS simulator. It can be noted that the improved performance offered by GaAs-FinFET is attributed to the greater mobility of charge carriers in addition to favourable material characteristics. Thus, it can be stated that the results obtained in the study prove that GaAs-FinFET is capable of becoming a viable alternative to existing silicon-based devices.
As an effective EMI suppression means, the spread spectrum modulation (SSM) technique introduces frequency variations that lead to drastic fluctuations in the output voltage of LLC resonant converters. In this paper, a dual-random-number interleaved spread spectrum modulation (DRNISSM) is proposed based on the analysis of power spectral density theory. The parameter design of DRNISSM is optimised by comparing and analysing the effects of different random frequency distribution types and key spread spectrum parameters on SSM results. Simulation and experimental verification on an LLC converter show that the output voltage under DRNISSM has a peak-to-peak value of 0.43 V and a ripple coefficient of 1.7%, with an improvement of 52% compared with the ripple of ordinary random SSM. At a spreading ratio of 8%, DRNISSM can reduce the conducted interference spectral peaks by nearly 10 dBV, with clearly better performance in the high-frequency band.
A flipped voltage follower (FVF) low dropout (LDO) regulator is proposed in this work for the load capacitor ranges of 400 pF to 10 nF. With load capacitor ranges of 400 pF to 10 nF, the proposed LDO can drive a peak load current of 20 mA while maintaining adequate stability margins. In this work, a simple single transistor discharge circuit is proposed that discharges the large load capacitor during the overshoot transient and reduces the settling time from mu s to ns. The enhanced super source follower (ESSF) presented in this work enhances the slew rate at the output of ESSF by providing increased bias current only during the transient and returning to normal after the transient. It also improves the DC gain of the LDO regulator. The proposed LDO uses two separate loops to improve the LDO regulator's performance. The frequency compensator reported in this paper combines two small compensating capacitors, a variable MOS resistor, and a feed-forward transistor to stabilize the LDO regulator's main loop. The proposed FVF LDO regulator is designed and realized using 130 nm CMOS technology. The proposed LDO regulator is stable, with a minimum phase margin of 50.4o for a load capacitor ranging from 400 pF to 10 nF and a peak load current of 20 mA. It achieves a settling time of 885 ns, even with the large load capacitor of 10 nF.
