Emphasis in this paper is on the fault ride- through operation impact on the wind turbines structural loads. Grid faults are typically simulated in power system simulation tools using simplified drive train mechanical model, approach which doesn't allow a thorough investigation of structural loads. This paper presents a two- steps simulation procedure, where two complimentary tools are combined, i.e. power system simulation tool and advanced aeroelastic simulation code. The goal is to investigate the whole integrated wind turbine design and to provide insight both into the structural as well as the electrical design of the wind turbine response during grid faults. The two-step simulation procedure is assessed by means of a simulation example. The effect of a grid fault on the structural part of a typical fixed speed wind turbine, equipped with an induction generator, is assessed.
— When performing short-circuit investigations in power systems including wind power, valuable and accurate results can only be obtained by considering the real behavior of wind turbines which is specified in national grid codes. This requires the consideration of the exact active and reactive current injections during the fault. In this paper an equivalent VSC-based wind turbine model for short-circuit calculations at steady-state conditions is developed and presented. The model is implemented in DigSILENT PowerFactory using the DPL-Programming Language. The developed wind turbine model is successfully evaluated proving that the DPL routine accurately implements the injection of the desired active and reactive current components according to the German grid code; the model is also compared with the validated 3.6MW variable-speed wind turbine dynamic model developed and provided by Siemens Wind Power. The wind turbine model is finally rescaled to obtain an aggregate wind farm model and used to perform short-circuit calculations in a realistic scenario; the Danish transmission system is considered and a large offshore wind farm with VSC-based wind turbines is included in the investigation.
Communication has always been a limiting factor in making efficient computing architectures with large processor counts. Reconfigurable interconnects can help in this respect, since they can adapt the interprocessor network to the changing communication requirements imposed by the running application. In this paper, we present a performance evaluation of these reconfigurable interconnection networks in the context of shared-memory multiprocessor (SMP) machines. We look at the effects of architectural parameters such as reconfiguration speed and topological constraints, and analyze how these results scale up with higher processor counts. We find that for 16 processors connected in a torus topology, reconfigurable interconnects with switching speeds in the order of milliseconds can provide up to 20% reduction in communication delay. For larger networks, up to 64 processors, the expected gain can rise up to 40%. This shows that reconfigurable networks can help in removing the communication bottleneck from future interconnection designs.
