The rapid deployment of AI across distributed edge-to-cloud environments in regulated sectors introduces significant big data security and governance challenges. This paper presents a secure and trustworthy AI pipeline integrating differential privacy in federated learning, attribute-based access control (ABAC), and blockchain-based auditability to protect sensitive distributed data and ensure accountable AI operations. The proposed framework is evaluated against major regulatory standards including GDPR, HIPAA, and SOC 2, and aligned with the EU AI Act and NIST AI Risk Management Framework. Experimental validation on a healthcare edge network with ten distributed nodes and a financial fraud-detection federation with five distributed nodes demonstrates over 94
This paper presents a framework for real-time synthetic X-ray image generation using FPGA-based hardware acceleration with High Bandwidth Memory (HBM). Synthetic image generation addresses the growing challenge of limited data availability by producing artificial images that closely resemble real ones. The work investigates the generation of synthetic X-ray images that can support equipment testing, physician training, and the creation of datasets for machine learning applications. Traditional synthetic X-ray generation relies on ray-tracing techniques executed on CPUs or GPUs. While accurate, these approaches are computationally intensive and require significant memory bandwidth. To address these challenges, the proposed approach leverages FPGA acceleration to efficiently handle the computational and memory demands of ray-tracing. The architecture simulates ray traversal through a voxelized model to compute attenuation maps that determine X-ray intensities at the detector. Computation is partitioned between a host system and an FPGA, while an optimized HBM-based memory architecture enables high data throughput. Measurements on an AMD Alveo U50 shows an average speed-up of 12x over the CPU baseline. Results show that the proposed design generates realistic images with only 2.26–3.00
In this paper we present an FPGA implementation of the ASCON-128 lightweight cipher employing a pipelined finite-state-machine design alongside a highly optimized sequential design. Experimental results demonstrate substantial improvements in throughput, silicon area utilization, and power consumption. Our novel pipelined FSM design on the Kintex-7 FPGA operates at an impressive frequency of 449.83 MHz while utilizing only 1067 slices and consuming 82 mW of power. In comparison, our sequential design achieves 289.85 MHz with 685 slices and 80 mW of power consumption on the same platform. In addition, we propose a cost-effective, high-performance hardware architecture designed to mitigate power analysis attacks. At its heart is a dynamic two-share masking scheme driven by a non-linear Fibonacci and Galois ring oscillator PUF-based true-random number generator. Compared with published FPGA implementations of ASCON-128, it outperforms state-of-the-art designs in both resource efficiency and power consumption. Our protected Kintex‑7 implementation achieves 399.98 MHz using 3155 LUTs (250 Mbps), utilizing 2.8 × fewer LUTs and delivering a 2.52 × higher operating frequency compared with the Kintex‑7 implementation reported in [16].
Provenance detectors commonly preserve anomaly evidence at event or graph level, whereas analysts investigate persistent entities and their causal relationships. This mismatch creates a representation gap between self-supervised prediction and investigation output. We introduce persistent node evidence as an investigation-oriented representation boundary for provenance streams. Each process, file, and network-flow identity maintains a fixed-width state updated from a bounded relational neighborhood, cumulative statistics, and elapsed time. Three self-supervised views test current-edge compatibility, recent target history, and within-window relation combinations, organizing decomposable event errors around long-lived entities. The representation is implemented with a compact 3.98 M-parameter neural core and bounded two-layer relational propagation without repeatedly encoding the accumulated provenance graph. Full-process memory additionally includes feature metadata and persistent runtime state. An optional normality-aware calibration learns recurring benign high-loss patterns from allowed normal roles and preserves raw and calibrated node rankings as separate views. Given a supplied investigation interval, a fixed provenance-constrained constructor expands ranked nodes into compact candidate chains. Across five Defense Advanced Research Projects Agency (DARPA) Transparent Computing collections, at least one candidate chain contains an exact annotated core or support identity in 12 of 13 successful attack chapters; the primary chain does so in eight. Complete scoring-process memory remains data dependent, calibration gains vary across collections, and the chain result measures conditional attribution rather than end-to-end attack discovery. The results support persistent node evidence as a bounded bridge from event prediction to precision-oriented offline investigation.
Current wireless environments are characterized by severe spectrum congestion and deliberate interference, exposing the limitations of traditional radio systems. This article presents an AI-enhanced software-defined radio (SDR) architecture implemented entirely on a field-programmable gate array and deployed on the PYNQ-Z2 platform, designed to perform real-time spectrum sensing and adaptive jamming mitigation. The proposed architecture implements an end-to-end processing chain comprising a 2048-point fast Fourier transform (FFT), log-power feature extraction, and a low-precision quantized neural network executed on the programmable logic with minimal processor involvement. Experimental results show an end-to-end latency of 2.1 ms, a classification accuracy of 94.5% at 5 dB signal-to-noise ratio, a jammer detection probability of 96.3% at a false-alarm rate of 0.05, and an energy consumption of 1.8 mJ per inference. Additional hardware security measures further enhance resilience against timing side-channel attacks and unauthorized access. These findings confirm that the proposed solution constitutes a compact, energy-efficient, and autonomous radio platform suitable for next-generation embedded defense systems.
