Vision Transformers (ViTs) have recently demonstrated superior accuracy compared to Convolutional Neural Networks (CNNs) in several computer vision tasks. Nevertheless, their deployment on resource-constrained edge devices remains challenging due to their high computational and memory demands. This work investigates the feasibility of Field Programmable Gate Array (FPGA)-based acceleration of General Matrix Multiplication (GEMM) layers in ViTs, where they represent the dominant computational workload, by means of a structured and parametric Design Space Exploration (DSE) methodology. These kernels are implemented using AMD Vitis HLS and optimized by varying key parameters (e.g., unrolling, pipelining, data precision, etc.). In parallel, the feasibility of representative ViT-related GEMM workloads, each defined by different matrix sizes and layer composition, is evaluated in terms of estimated FPGA resource usage and latency. The resulting hardware configurations are evaluated on two target FPGA platforms with different resource profiles: the AMD Kria KV260, representative of edge-oriented devices, and the more resource-rich AMD ZCU102. The proposed DSE aims to untangle the large number of possible configurations and their complex trade-offs among resource usage, latency, and numerical precision. To address this challenge, an Artificial Intelligence (AI)-based predictive search method is proposed to identify the most suitable implementation that minimizes latency while meeting target precision settings and resource constraints. The proposed approach achieves prediction errors comparable to state-of-the-art methods and shows the feasibility limits of deploying ViT-related GEMM workloads on FPGA-based edge devices.
In early stages of prototyping and acceleration, designers rely on vendor-specific and architecture-specific resource metrics (e.g., LUTs, ALMs, DSP blocks), which prevent direct cross-platform comparison and complicate design space exploration. We present MARU (Machine Learning-based Approaches for Resource-to-Area Estimation), a framework that predicts ASIC-like physical area directly from FPGA resource utilization estimates (e.g., post-HLS or synthesis reports). MARU achieves an average of 4
This paper introduces JACABench, the JACA Benchmark Suite for embedded computing systems. JACABench is a C-based benchmark suite designed to complement existing evaluation frameworks. JACABench incorporates a set of features that support the systematic assessment of compilers, code transformations and optimizations, high-level synthesis (HLS) tools, hardware accelerators, and embedded computer architectures, as well as the impact of code variants on performance and energy consumption. For each benchmark, the suite provides multiple code variants that capture relevant dimensions, including alternative code transformations, data types, scenario-specific specializations, and configurable parameters. JACABench is conceived as a continuously evolving benchmark suite, with a particular emphasis on FPGA-based embedded computing. We present the initial set of benchmarks currently included in the suite and show the impact of selected code variants on FPGA implementations.
Recent advances in hardware architectures enable real-time, low-latency, and energy-efficient computation capabilities that are essential in medical applications where timely and reliable decisions can directly affect patient outcomes. While traditional Artificial Intelligence (AI) approaches such as Convolutional Neural Networks (CNNs) and Deep Neural Networks (DNNs) have shown strong performance in biomedical signal analysis, their reliance on computationally intensive operations often limits deployment in low-power, resource-constrained medical devices. This paper presents a lightweight hardware accelerator for real-time detection and classification of cardiac arrhythmias from electrocardiogram (ECG) signals using Weightless Neural Networks (WNNs). The proposed architecture leverages an ensemble of Wilkie–Stonham–Aleksander Recognition Device (WiSARD)-based classifiers, replacing conventional weight-based computation with RAM-based storage. Multi-threshold binarization is used to extract discriminative ECG features across multiple intensity levels, while a tie-breaking mechanism improves robustness during ensemble decision-making. The complete design is implemented in synthesizable SystemVerilog and validated through functional simulation. The proposed model achieves 92.57
In real-time applications such as obstacle avoidance in mobile robots, environmental perception systems need to continuously provide reliable object state information in dynamic scenarios. Multi-object tracking (MOT) lies on the critical path between perception and decision-making, and its processing latency directly impacts system responsiveness, particularly in scenes with dense targets or rapid motion. Compared with software implementations on general-purpose processors, Field Programmable Gate Arrays (FPGAs) provide architectural support for parallel processing and predictable timing behavior. This paper presents a hardware-oriented analysis and implementation of the classical Simple Online and Realtime Tracking (SORT) algorithm. The key computational components are restructured to improve hardware efficiency, and a complete tracking pipeline is subsequently implemented for FPGAs. The proposed design aims to enhance both computational efficiency and timing determinism in the MOT stage, enabling low-latency and predictable execution for downstream decision-making modules. Experimental results show that the proposed FPGA solution achieves up to 100 × speedup over the embedded software implementation under identical input conditions. Moreover, across different scenarios and object counts, the FPGA design maintains a significantly narrower latency distribution than the software baseline. These results confirm that the proposed approach delivers both high computational performance and stable timing behavior.
The increasing diffusion of cyber-physical systems and Internet of Things applications demands computing infrastructures capable of handling large data volumes under strict latency, scalability, and energy constraints. Traditional cloud-centric approaches are often inadequate for such requirements, motivating the adoption of the computing continuum paradigm, which integrates edge, fog, and cloud resources. This paper presents a preliminary assessment of the MYRTUS project, a Horizon Europe initiative aimed at enabling seamless orchestration across heterogeneous computing infrastructures. The MYRTUS architecture combines a distributed infrastructure, an AI-driven orchestration engine, and a dedicated development environment to support adaptive applications. A demonstrator based on UAV navigation in GPS-denied environments is introduced to evaluate the infrastructure. The application distributes processing tasks across continuum layers, leveraging edge devices for real-time operations and cloud resources for intensive computation. Results highlight the potential of MYRTUS to support efficient, scalable, and energy-aware execution of complex distributed applications.
Sizing intermediate data buffers has been a long-standing challenge in building FPGA dataflow accelerators. Current techniques rely on imperfect analytical models or time-intensive simulation, often choosing suboptimal buffer sizes, which either waste valuable resources or risk performance degradation. We introduce an FPGA-accelerated buffer-sizing approach that finds locally optimal first-in-first-out (FIFO) buffer sizes by synthesizing and profiling a lean but faithful surrogate of the target dataflow design. Contrary to existing simulation-based or model-based techniques, our approach guarantees optimal throughput and latency results using a search-based fine-tuning step, which is enabled by our ability to evaluate any FIFO depth configuration five orders of magnitude faster than in simulation. We fully integrate our approach into the open-source deep neural network (DNN) accelerator compiler FINN and evaluate it on a suite of 12 example DNNs, achieving a total FIFO size reduction of up to 86
Deploying robust adaptive beamforming (RABF) algorithms on Unmanned Aerial Vehicle (UAV) swarm radars presents a severe conflict between anti-jamming performance and hardware efficiency. Traditional RABF algorithms demand high-precision continuous floating-point weights, necessitating numerous power-hungry hardware multipliers (e.g., DSP slices on FPGAs) during the high-speed real-time spatial filtering stage. This is highly detrimental to the stringent Size, Weight, and Power (SWaP) constraints of edge UAVs. While naive single-shift Power-of-Two (PoT) quantization mitigates multiplier usage, it inevitably suffers from severe null-shallowing effects, failing to suppress strong active jammers. In this paper, we propose a multiplier-free hardware/algorithm co-design: the Double-Shift PoT RABF. By mapping the complex weights to a meticulously designed double-shift discrete dictionary, our approach entirely eradicates multipliers in the data path, substituting them with energy-efficient programmable bit-shifters and adders. We formulate the discrete optimization problem using the Alternating Direction Method of Multipliers (ADMM) framework to guarantee deep jamming nulls. Extensive simulations demonstrate that under UAV position perturbations, the proposed multiplier-free method exhibits nearly zero performance degradation (less than 0.1 dB SINR loss) compared to the traditional 32-bit floating-point baseline, offering a highly hardware-efficient solution for next-generation UAV edge computing.
Accurate and energy-efficient recognition of swimming styles is essential for real-time training analysis in wearable systems. This work introduces an end-to-end, spike-driven approach for swimming style classification, in which a Spiking Neural Network (SNN) operates on event-based inertial inputs. To the best of our knowledge, this is the first application of neuromorphic computing to swimming style recognition. The signal encoding employs delta modulation on accelerometer, gyroscope, and magnetometer axes, converting continuous sensor streams into sparse binary spike trains that capture temporal dynamics of swimming movements without requiring explicit filtering or feature extraction. A compact fully connected SNN with leaky integrate-and-fire neurons classifies four swimming styles (freestyle, breaststroke, backstroke, and butterfly) using only 18,176 trainable parameters. The approach is validated on a publicly available benchmark of 40 swimmers recorded in realistic training conditions, achieving an F1 of 0.945 under Leave-One-Subject-Out cross-validation. To support deployment on resource-constrained wearable devices, we implement an optimized hardware architecture on a low-power Lattice iCE40-UltraPlus FPGA. The event-driven nature of the SNN enables efficient inference by processing only active spikes, reducing power consumption while maintaining low latency. Performance evaluations indicate an execution time of 7.8 ms per classification, with energy usage of 93.6 J, demonstrating the feasibility of on-device real-time swimming analysis.
Reconfigurable computing bridges the gap between the flexibility of general-purpose processors and the efficiency of application-specific hardware. Among reconfigurable architectures, Coarse-Grained Reconfigurable Arrays (CGRAs) are particularly promising because they offer high efficiency and low configuration overhead, while maintaining programmability at the operation level. However, mapping high-level applications onto CGRAs remains challenging, as most state-of-the-art approaches either have a limited compilation scope or incur a very high compilation time. To address this challenge, we propose a compilation framework that supports generic control–dataflow graphs by scheduling dataflow graphs under explicit control-flow constraints. The framework adopts a flexible approach that comprises a fast heuristic mapping strategy for non-critical code regions, while enabling aggressive optimizations for performance-critical regions. Experimental results show up to 10 × faster compilation for applications with complex control–dataflow graph structures, while achieving comparable or better runtime performance relative to existing approaches.
Applied Reconfigurable Computing (ARC) is evolving from kernel-level hardware acceleration toward distributed adaptability across heterogeneous infrastructures. Contemporary edge-centric systems operate under dynamic constraints of latency, energy variability, security, and scalability, requiring coordinated structural adaptation across sensing nodes, edge gateways, and cloud platforms. This paper presents the architectural framework developed within the H2TRAIN collaborative project as an implementation of hierarchical reconfiguration across the edge–cloud continuum. Although deployed in health-oriented scenarios, the architectural contribution is domain-agnostic and generalizable. The proposed architecture distributes configurable signal processing, adaptive AI execution, service-level redeployment, secure remote management, and multi-cloud orchestration across sensing subsystems, a programmable edge gateway, and cloud services. Reconfiguration occurs at hardware, runtime, and infrastructure levels, illustrating how reconfigurable computing extends beyond accelerator design and becomes a systemic property of distributed intelligent systems.
Traditionally, a primary goal of technology mapping for K-input lookup-tables (LUTs) is depth minimization. A typical approach is to make cuts in a Boolean network such that the logic of each cut fits into a single LUT, and thus cover the entire graph. Many different cuts can potentially be mapped into a LUT and finding the optimal cut has a very high complexity. The widely used priority cuts algorithm only stores a small fixed number of cuts per node during the mapping, the so-called priority cuts, yet produces very good results at a comparatively low runtime. In this work, the priority cuts algorithm is examined using the well-known EPFL benchmark set. A number of these benchmarks are significantly larger than those used in the original paper, enabling an analysis of the mapping quality that better represents modern requirements. In particular, the performance is compared to exhaustive cut enumeration, while focusing on the achieved depth. The insights obtained are applied to a recent extension of the priority cuts algorithm that uses the Ashenhurst-Curtis decomposition to effectively utilize larger cuts, which can not be directly implemented by a single LUT, during mapping. As a result, three new records are set in terms of depth in the ongoing EPFL competition. To alleviate the increased runtime from storing more cuts per node, a method of sorting the cuts before attempting the decomposition is introduced. This procedure roughly halves the runtime for a given number of cuts stored per node while maintaining the result quality.
Online continual learning (CL), where a model must learn new tasks sequentially without forgetting prior ones, is a fundamental capability for adaptive edge AI systems. Elastic Weight Consolidation (EWC) is among the most principled algorithmic approaches, using the Fisher information matrix to identify and protect task-critical parameters, but its per-task Fisher computation incurs a 4.7× runtime overhead over standard fine-tuning that makes it impractical on embedded CPU platforms. We present StreamLearn-FPGA, a dedicated hardware architecture for EWC-based continual learning targeting the Xilinx Zynq UltraScale+ ZU3EG SoC. StreamLearn-FPGA introduces three architectural innovations: (1) a pipelined Importance Scoring Unit (ISU) that computes per-parameter Fisher diagonal estimates at 41.7 M parameters/second, (2) a Gated Update Engine (GUE) that enforces EWC parameter protection in hardware at 12.4 ns per parameter, and (3) an Elastic Threshold Controller (ETC) that automatically adjusts the regularisation penalty λ based on running task-loss trajectories. Evaluated on a 10-task sequential classification scenario with a 0.5M-parameter CNN on the ZCU104 board, StreamLearn-FPGA achieves 8.2× faster per-task training and 7.2× lower energy versus EWC-CPU, while delivering 84.58 12.9× PackNet’s speed. The design occupies 38.4
Modern processor performance is strongly constrained by the memory hierarchy and memory access patterns, and this sensitivity is particularly pronounced for FPGA-based soft-core CPUs with configurable memory subsystems. This paper presents a systematic experimental study of how physical memory access patterns interact with DRAM controllers and cache hierarchies to shape the performance of RISC-V soft cores on FPGA platforms with DDR4 memory. We evaluate representative access patterns including row-major sequential, column-major, small and large strides, and blocked traversal across STREAM kernels, dense matrix multiplication and transpose, and vector reduction workloads. The analysis compares an in order Rocket core and an out-of-order BOOM core instantiated on a Xilinx VCU118 board, using only standard RISC-V hardware performance counters to ensure portability. Row-major scans attain up to 163.91 MB/s on BOOM, while column-major traversal and large strides can increase per-element execution cost by up to 68 × speedup for matrix multiplication by keeping working sets within the 32 KB L1 cache, largely independent of core microarchitecture. Contrary to the common assumption that out-of-order cores are always more sensitive to memory pressure, we find that BOOM’s overhead can be higher or lower than Rocket’s depending on the workload, despite identical L1 caches and DRAM interfaces. The proposed microbenchmark suite and methodology form a reproducible framework for characterising memory-subsystem behavior of FPGA-based RISC-V systems and provide practical guidelines for designing locality-aware kernels on reconfigurable platforms.
LUT-based DNN accelerators offer ultra-low latency FPGA inference, but their adoption is severely constrained by excessive resource consumption. This paper introduces CLAS, a cross-layer approximation framework for LUT-based DNNs that redefines approximation in fully unrolled networks by (i) treating neurons as substitutable RTL components and (ii) jointly exploring combinations of approximated layers at the RTL across the network. The proposed framework effectively combines algorithmic-level approximations, including sensitivity-driven pruning and quantization, with a library-based RTL approximation strategy to enable cross-layer optimization. Key stages of CLAS, including neuron library construction and two-level design space exploration (DSE), are fully parallelized, enabling scalable exploration of large approximation spaces that would otherwise be computationally impractical. Our combined layer- and network-level DSE strategy effectively evaluates a diverse range of approximate layer combinations, globally optimizing accuracy–area trade-offs under strict constraints. CLAS achieves substantial LUT reductions with a small accuracy loss, outperforming algorithmic-level approximation baselines by delivering an additional 32.6
This paper introduces a novel divide-and-conquer approach to optimize a neural network ensemble. The approach would optimize the available resources to implement multiple neural networks in the ensemble. Three algorithms are proposed to explore the structure of neural networks and to estimate the optimal parallelism configuration for an ensemble; they provide a configuration design guide to facilitate the study of trade-offs between resource usage and run time. Our approach also supports variable widths of input data, further improving the diversity of the ensemble. The proposed approach shows promise in the evaluation against related work and baseline implementations, especially when used to process input data streams, with the ensemble utilizing the available resources to achieve 33 times speed up with 10
Modern sensors and IoT devices enable exciting applications but they also face challenges, especially due to data movement bottlenecks to the Cloud. Pushing down processing to the sensors or the Edge can help alleviate these bottlenecks, but it is an open question what types of processing elements are best for this purpose. As many related works show, FPGAs are a promising option due to their predictable behavior, streaming execution semantics, and energy efficiency. However, placing accelerators such as datacenter-grade FPGAs or GPUs right next to sensors, that are often battery operated, or at power-constrained Edge nodes is not practical. Instead, in this work we show that, using the right design approach, it is feasible to implement anomaly detection algorithms with small FPGAs suitable for energy-limited deployments – and this creates exciting new opportunities in using FPGAs for data pre-processing at the Edge.
This paper presents the development and implementation of a neuromorphic robot controller on a Field-Programmable Gate Array (FPGA) designed to support smooth, spiking neural network (SNN)-based trajectories. Utilizing the ED-Scorbot framework, the system controls a Scorbot ER-VII robotic arm with six degrees of freedom through an event-driven proportional-integral-derivative (SPID) architecture. Unlike traditional robotic control, this approach employs Pulse Frequency Modulation (PFM) to drive DC motors, mimicking biological motor neuron activation. The controller is synthesized within the Programmable Logic (PL) of a Xilinx Zynq 7100, while the Processing System (PS) manages configuration via MQTT protocols and remote connectivity. Our results demonstrate that the spike-based processing architecture is highly efficient, consuming only 4.8
Direct current (DC) series arc fault detection is a critical task in electrical safety systems, demanding high detection accuracy, low inference latency, and energy efficiency. Convolutional neural networks (CNNs) have shown strong potential for identifying arc fault patterns. However, their efficient deployment on embedded hardware platforms remains an open research challenge. The AI Engine–Machine Learning (AIE-ML), an ML-optimized variant of the AI Engine array in Versal adaptive SoCs, is well suited to these requirements, offering a programmable, vector-centric compute fabric tailored to the constraints of edge devices. To fully exploit this architecture, we develop STANN-AIEML, an open-source hardware–software co-design workflow that enables efficient inference of deep learning models on the Versal AI Edge platforms. The proposed framework streamlines the mapping and optimization of neural networks onto AIE-ML-based architectures, facilitating high-performance and rapid deployments in resource-constrained environments. This study presents a CNN-based approach for efficient DC series arc fault detection, accelerated on an AMD Versal VE2302 device. By leveraging the STANN-AIEML library, we address key challenges in deploying CNN models on Versal AI Edge devices. The proposed CNN model is fine-tuned to achieve high detection accuracy while maintaining low inference latency. Furthermore, a comprehensive analysis and comparison with state-of-the-art implementations on FPGA and GPU platforms demonstrate the performance advantages of the proposed AIE-ML–accelerated solution. This work advances real-time, low-latency arc fault detection and contributes toward safer and more reliable DC electrical systems across a wide range of industrial applications.
