Vision Transformers (ViTs) have recently demonstrated superior accuracy compared to Convolutional Neural Networks (CNNs) in several computer vision tasks. Nevertheless, their deployment on resource-constrained edge devices remains challenging due to their high computational and memory demands. This work investigates the feasibility of Field Programmable Gate Array (FPGA)-based acceleration of General Matrix Multiplication (GEMM) layers in ViTs, where they represent the dominant computational workload, by means of a structured and parametric Design Space Exploration (DSE) methodology. These kernels are implemented using AMD Vitis HLS and optimized by varying key parameters (e.g., unrolling, pipelining, data precision, etc.). In parallel, the feasibility of representative ViT-related GEMM workloads, each defined by different matrix sizes and layer composition, is evaluated in terms of estimated FPGA resource usage and latency. The resulting hardware configurations are evaluated on two target FPGA platforms with different resource profiles: the AMD Kria KV260, representative of edge-oriented devices, and the more resource-rich AMD ZCU102. The proposed DSE aims to untangle the large number of possible configurations and their complex trade-offs among resource usage, latency, and numerical precision. To address this challenge, an Artificial Intelligence (AI)-based predictive search method is proposed to identify the most suitable implementation that minimizes latency while meeting target precision settings and resource constraints. The proposed approach achieves prediction errors comparable to state-of-the-art methods and shows the feasibility limits of deploying ViT-related GEMM workloads on FPGA-based edge devices.
In early stages of prototyping and acceleration, designers rely on vendor-specific and architecture-specific resource metrics (e.g., LUTs, ALMs, DSP blocks), which prevent direct cross-platform comparison and complicate design space exploration. We present MARU (Machine Learning-based Approaches for Resource-to-Area Estimation), a framework that predicts ASIC-like physical area directly from FPGA resource utilization estimates (e.g., post-HLS or synthesis reports). MARU achieves an average of 4
This paper introduces JACABench, the JACA Benchmark Suite for embedded computing systems. JACABench is a C-based benchmark suite designed to complement existing evaluation frameworks. JACABench incorporates a set of features that support the systematic assessment of compilers, code transformations and optimizations, high-level synthesis (HLS) tools, hardware accelerators, and embedded computer architectures, as well as the impact of code variants on performance and energy consumption. For each benchmark, the suite provides multiple code variants that capture relevant dimensions, including alternative code transformations, data types, scenario-specific specializations, and configurable parameters. JACABench is conceived as a continuously evolving benchmark suite, with a particular emphasis on FPGA-based embedded computing. We present the initial set of benchmarks currently included in the suite and show the impact of selected code variants on FPGA implementations.
Recent advances in hardware architectures enable real-time, low-latency, and energy-efficient computation capabilities that are essential in medical applications where timely and reliable decisions can directly affect patient outcomes. While traditional Artificial Intelligence (AI) approaches such as Convolutional Neural Networks (CNNs) and Deep Neural Networks (DNNs) have shown strong performance in biomedical signal analysis, their reliance on computationally intensive operations often limits deployment in low-power, resource-constrained medical devices. This paper presents a lightweight hardware accelerator for real-time detection and classification of cardiac arrhythmias from electrocardiogram (ECG) signals using Weightless Neural Networks (WNNs). The proposed architecture leverages an ensemble of Wilkie–Stonham–Aleksander Recognition Device (WiSARD)-based classifiers, replacing conventional weight-based computation with RAM-based storage. Multi-threshold binarization is used to extract discriminative ECG features across multiple intensity levels, while a tie-breaking mechanism improves robustness during ensemble decision-making. The complete design is implemented in synthesizable SystemVerilog and validated through functional simulation. The proposed model achieves 92.57
