Power consumption is a crucial design aspect in multimedia and machine learning applications. Approximate computing offers an energy-efficient approach for both power reduction and area optimization. In this paper, a hybrid approximation methodology based on error tolerant multipliers (ETMs) is introduced. The proposed design splits the approximation process into two parts: (1) approximating the most significant bits (MSBs) using approximate logarithms and (2) approximating the least significant bits (LSBs) using truncation. A prototype of the proposed multiplier is demonstrated with an image processing application (JPEG compression) using a Discrete Cosine Transform (DCT) where the power delay product (PDP) is improved by 1.9X. And the area utilization is reduced by 2.7X with only 20% reduction in the output image peak signal-to-noise ratio (PSNR).
Stepper motors are widely employed in several daily applications, since their use is quite simple. Typically, a microcontroller (or a similar digital device) generates pulse-bursts and a direction bit to control a commercial power driver that produces the 2-phase currents feeding the motor windings. Despite its simplicity, this open-loop solution is sensitive to load variation and fails severely if the torque load exceeds the motor capacity. Closed-loop solutions based on Field-Oriented Control (FOC) solves the problem. However, they require heavy calculations and a dedicated hardware to control the motor currents. In this paper, a closed-loop solution is presented that avoids heavy calculations and demands the motor currents generation to the same commercial driver typically used for open-loop solutions. A low-cost Field Programmable Gate Array (FPGA) implements the algorithm and connects to the commercial power driver through the standard 2-signal interface (pulse-burst / direction bit). Experiments with a 1.1 Nm, two phases, 200-step/revolution hybrid stepper motor show the performance of the proposed method in a constant torque condition and during a position step movement.
We propose a task allocation and scheduling (TAS) optimization for the varying execution time tasks in the heterogeneous core system. It utilizes the additional dependency called waiting dependency and optimizes the core type assignment by simulated annealing. We confirm that the proposed method improves the scheduling performance, empirically.
Modern power electronic circuits typically require an on-board microcontroller to carry out necessary sensor measurements and controlled semiconductor switching. Hence, in the prototyping stage it is convenient to have a microcontroller development board designed for noise immunity and best electromagnetic compatibility possible. Typical development boards provided by manufacturers are not designed to such a specification due to cost considerations. This paper presents the design of an improved development board for the STM32F4 microcontroller for better performance in switching power converter circuits.
In the fields of machine learning and image processing, cost-less circuits with low energy are required instead of extreme precision, and stochastic computing (SC), a type of approximate computing, is attracting attention. In SC, stochastic numbers (SNs), bit streams with values of the appearance rates of 1`s, are used. SC enables calculations with simple circuits. To make the calculation results correct, duplication of an SN (gener-ating an SN with the same value) is required when using the SN with the same value. The conventional SN duplicator composed of a flip-flop (FF) has a problem that the output SN only depends on the input SN. Therefore, if the FF-based duplicator is used in a circuit with re-convergence paths, the output SN becomes erroneous. This paper proposes an SN duplicator, 2 n RRR, that can output more independent output by its improved flexibility of bit re-arrangement. With this duplicator, the errors of the hyperbolic tangent function are reduced by up to 50% compared to the duplicator that we proposed previously. Also, up to more than 99.9% of the circuit area is reduced compared to the implementation of binary computing.
