Increasing complexity of digital and mixed-signal systems makes establishing the authenticity of a chip to be a challenging problem. We present a new terahertz testing technique for non-destructive identification of genuine integrated circuits, in package, in-situ and either with no or under bias, by measuring their response to scanning terahertz and sub-terahertz radiation at the circuit pins. This novel, patent pending non-invasive nondestructive technology when merged with Artificial Intelligence (AI) engine will evolve and self-improve with each test cycle. By establishing and AI processing of the THz scanning signatures of reliable devices and circuits and comparing this signatures with devices under test using AI, this technology could be also used for reliability and lifetime prediction.
This work presents various device self-heating temperature sensing techniques and discusses their application in device reliability projection. Details of sensor design, technology choice, layout and ambient temperature impact on measurement results are discussed. The sensors produce excellent results which were confirmed through TCAD thermal simulation. Self-heating was studied by varying the number of fins per active region and proximity of sensor to heater was investigated. While most data presented here is on FinFET technology the learning and measurement techniques are applicable to planar technologies. Front-end-of-line (FEOL) reliability mechanism, hot carrier injection (HCI) was studied to show that self-heating effects can impact measurement results and recommendations are given on how to mitigate them. Self-heating is also studied for logic circuits by utilizing ring oscillators with several densities and stage counts to show that self-heating is considerably lower compared to constant voltage stress conditions conducted on discrete structures.
The power limits due to thermal runaway of a germanium PIN photodiode as the O-band $(\lambda\sim\mathbf{1300\ nm})$ photodetector component of a silicon photonics technology were characterized under elevated stress conditions. A simplified model is used to project to use condition.
We introduce a new Build In Test (BIT) signature generator for functional verification and output classification of RF integrated circuits. The proposed circuit is a single rectifier-based MOS transistor, with the substrate and gate independently biased to control source terminal voltage range, followed by a passive RC filter. The proposed technique correlates the Circuit Under Test (CUT) characteristics with the dc voltage provided at the output of the BIT circuit. The output from the proposed circuit is used as signature from which we verify the performance specifications and also characterize the CUT output waveform with respect to amplitude and shape. In normal operation the proposed low cost test scheme ensures the minimum effect at the performance of the measured circuit under test since the only additional load is the source of the MOS transistor attached to it.
In-memory computing is a propitious solution for overcoming the memory bottleneck for future computer systems. In this work, we present the testing and validation considerations for a programmable artificial neural network (ANN) integrated within a phase change memory (PCM) chip, featuring a Nor-Flash compatible serial peripheral interface (SPI). In this paper, we introduce our method for validating the circuit components specific to the ANN application. In addition, high-density in-memory multi-layer ANNs cannot be manufactured without testing and repair of the memory array itself. Therefore, design for testability (DFT) features commonly used in commodity or embedded memory products must be maintained as well. The combination of these two test/characterization steps alleviates the need to test the actual inference functionality in hardware.
