OpenVADL is an open source implementation of the Vienna Architecture Description Language (VADL). VADL is a processor description language (PDL) that enables the concise formal specification of processor architectures. OpenVADL automatically generates an assembler, an LLVM based compiler and a QEMU based instruction set simulator from a single VADL processor specification. Automatic generation of synthesizable specifications in a hardware description language is under development. VADL strictly separates the instruction set architecture (ISA) specification from the microarchitecture (MiA) specification. VADL’s MiA specification operates at a higher level of abstraction compared to existing PDLs. This article introduces OpenVADL, describes the generator techniques in detail and shows the performance of the generators in an empirical evaluation. The evaluation demonstrates the capabilities of OpenVADL and its efficiency. An OpenVADL generated instruction set simulator is up to 77
A Flash Translation Layer (FTL) hides the intrinsic flash properties of SSDs and provides a block interface to the host. FTLs completely embedded in the firmware of SSDs must therefore duplicate host functionality, such as the translation between logical and physical blocks performed by a file system, introducing performance unpredictability and increasing device cost. Zoned Namespace (ZNS) SSDs overcome these drawbacks by only implementing limited FTL functionality inside the SSD and by exposing a more flash-friendly interface to the host. However, moving away from the block interface means that the storage stack inside the host must be modified for ZNS devices. This requires considerable effort, which is one reason why F2FS is the only Linux file system with reliable ZNS support today. This paper discusses how the Linux storage stack can be extended to simplify the process of adapting file systems to ZNS devices. It then proposes the host-side Zoned Translation Layer (ZTL), which provides abstractions and functionalities required by many file systems to support ZNS devices. We demonstrate the feasibility of ZTL by providing the first EXT4 implementation for ZNS devices and by comparing our implementation of ZNS support for F2FS with the native ZNS support of F2FS.
In this paper, a new 2-bit error correcting (DEC) linear code is presented as a modification of a corresponding 2-bit error correcting (DEC) BCH code. Compared to an unchanged BCH code in GF(2^m) with 2· m check bits and a code length of 2^m-1 , the number of data bits can be increased by at least m+1 bits. The number of check bits only needs to be increased by 1. New columns and a single new row are added to the parity check matrix of the unchanged BCH code. The added columns are determined according to the columns of a parity check matrix of any 2-bit error correction code with only m check bits. The bits of the added row distinguish between the columns of the unchanged BCH code and the columns of the added columns. The proposed method is particularly interesting for longer code lengths. Decoding remains simple even with long code lengths, as the known algebraic methods for decoding BCH codes can be used for most of the bits. A small look-up table is only required for the relatively small number of bits added.
Fuzzy spatial relations are increasingly utilized in visual reasoning tasks, such as semantic annotation and object recognition. However, these tasks often rely on compute-intensive fuzzy morphological operators, leading to significant latency during relation evaluation. Addressing this challenge requires optimized implementations that are tailored to modern architectures. Previous works introduced the Reverse (R) and Parallel Reverse (PR) algorithms for Intel processors, leveraging OpenMP and SIMD intrinsics. In this work, we extend these contributions to embedded systems by targeting ARM-based processors and NVIDIA embedded GPUs. Specifically, we propose three architecture-specific implementations: PR64N, using 64-bit NEON SIMD instructions; PR128N, using 128-bit NEON instructions; and PRGPU, a GPU-optimized version based on CUDA. Our evaluation is conducted on the NVIDIA Jetson Orin Nano Super platform, an advanced ARM-based system-on-chip designed for low-power edge AI applications. The results demonstrate that our CPU implementations achieve near-peak performance by fully exploiting the platform's memory bandwidth. Meanwhile, the GPU implementation efficiently offloads fuzzy spatial relation evaluations, allowing the CPU to manage additional workloads. These findings underline the suitability of our methods for enabling visual reasoning tasks on resource-constrained embedded systems and contribute to the broader discussion on addressing heterogeneous architectures with tailored algorithms.
Self-Adaptive and Self-Organizing (SASO) systems aim to tackle the challenges of information technology's growing complexity. While various control patterns exist to coordinate such systems, this Ph.D. project takes a fully centralized perspective as its starting point. The focus lies on developing a Central Control Unit (CCU) capable of multi-objective, self-aware optimization while balancing potentially conflicting local decisions. As part of the InHOSaS project, this research, along with a second Ph.D. project, will ultimately integrate the CCU with autonomous decision-making at the subsystem level, forming a hybrid approach. These methods are exemplified using the platooning use case, demonstrating the coordination of semi-automated or automated vehicles within the SASO framework to maintain both individual subsystem goals and overarching system constraints.
