This work investigates the effect of scaling on the electrostatic behavior of cross‐shape reconfigurable field‐effect transistors (RFETs) using three‐dimensional technology computer‐aided design simulations. The emerging device concept consists of multiple nanowires in a junction of a common channel, where multiple gates are aligned on the silicon and silicide junction interface, enabling polarity switching and signal routing within a compact layout. Although such a geometry can be utilized for new directions in neuromorphic or analog computation, it significantly increases the electrostatic interactions. The focus of the work is to understand the impact of the gate‐to‐gate distance and nanowire width on the on‐state current. The energy barrier in the ungated common‐channel region was found to be the limiting factor, as excessive fringing field coupling at short gate‐to‐gate distances causes electrostatic crowding and barrier sharpening, thereby restricting carrier transport. To overcome the electrostatic limitation of the cross‐shape RFET, a three‐dimensional U‐shape RFET was proposed. Due to its gate‐all‐around coverage of the metal–semiconductor junctions, electrostatic control was found to be stronger. U‐shape geometry achieves a high on‐state current with a minimal sensitivity to gate‐to‐gate distance variations. This work derives practical design guidelines for 3D RFET architectures, aiming to balance device compactness and electrostatic efficiency.
This article proposes a novel high electron mobility transistor (HEMT) device with a triple‐barrier‐layer (TBL‐HEMT) structure of AlGaN. The conventional 15 nm single AlGaN barrier is divided into three sublayers with Al compositions of 0.25, 0.20, and 0.15 from top to bottom. In order to enhance radio frequency (RF) performance, a 1 μm linearly graded AlGaN underlying layer is employed to efficiently suppress short channel effect during device scaling. Three types of stacked passivation films including HfO 2 /SiO 2 , Al 2 O 3 /SiO 2 , and SiO 2 /SiO 2 are analyzed, and a 100 nm air gap near the gate helps cut parasitic gate capacitance greatly. The optimized SiO 2 /SiO 2 (air = 100 nm) scheme delivers the highest cutoff frequency ( f T ) of 114 GHz. The device under consideration in this article demonstrates a high cutoff frequency, excellent direct current performance, and a very high RF quality factor. These characteristics offer substantial reference value for future applications in the domain of RF electronics.
This paper presents a finite element analysis study on the impact of material selection and sensor geometry on the performance metrics of a microelectromechanical systems piezoresistive readout‐based pressure sensor for biomedical applications. The pressure sensor dimensions are designed for housing in a typical 5Fr catheter utilized for in vivo biomedical applications. In this work, focus is on devising a rational selection of piezoresistor material and sensor geometry for maximizing performance metrics of the sensor. For investigation, we have considered three generations of piezoresistive materials which exhibit a wide range of gauge factors. Subsequently, the study explores different sensor mechanical diaphragm geometries, focusing on stress distributions, displacements, and variations in resistance governing sensitivity and structural nonlinearity. Simulation results show that for constant resonant frequency and fixed piezoresistors, among the sensor geometries, circular geometry of sensor platform depicts the highest electrical sensitivity. Among piezoresistor materials, gold has the lowest sensitivity (1.229 × 10 −4 ), confirming its weak piezoresistive nature. P‐type silicon demonstrates moderate sensitivity, reaching up to (6.779 × 10 −4 ). On the other hand, response of graphene nanoplate SU‐8 is the highest (9.501 × 10 −4 ). Results show that nonlinearity errors for square, octagonal, and circular geometries are −0.637%, −0.431%, and −0.420%, respectively, within a pressure range of 0–100 mmHg.
Layered transition‐metal dichalcogenides (TMDs) have emerged as an incipient class of low‐dimensional quantum materials owing to their highly tunable electronic, optical, magnetic, and catalytic properties. In recent years, controlled electronic modulation through substitution, intercalation, surface doping, and interstitial doping has become an effective strategy for tailoring the intrinsic physical properties, introducing extra degrees of freedom and inducing emergent quantum phenomena in TMD single crystals. This review summarizes recent progress in electronically modulated layered TMD single crystals synthesized primarily via chemical vapor transport (CVT) methods. Particularly emphasizing on different heteroatomic incorporation strategies and their influence on crystal structure, charge transfer, band structure evolution, magnetic ordering, topological properties, charge‐density waves, and phase transitions. Advanced characterization techniques including synchrotron‐based X‐ray spectroscopies, X‐ray photoelectron spectroscopy, scanning tunneling microscopy, scanning transmission electron microscopy, and angle‐resolved photoemission spectroscopy are discussed in detail for understanding the structural and electronic modifications induced by electronic modulation. Furthermore, the correlation between electronic structure engineering and resultant transport, magnetic, and optoelectronic properties is highlighted alongside recent advances in device‐oriented applications. Finally, the review discusses current challenges, post‐treatment strategies, and future perspectives for designing next‐generation electron‐modulated 2D quantum materials for electronic, spintronic, and quantum technologies.
A detailed study of a charge plasma cylindrical gate‐all‐around (CP‐GAA) vertical nanowire (NW) tunnel field‐effect transistor (TFET) based on technology computer‐aided design (TCAD) is presented with effects of interface trap density ( D it ) on the device DC, analog, and RF characteristics. The device relies on an intrinsic silicon nanowire of 5 nm radius and 50 nm gate length and platinum and hafnium contacts to create hole‐ and electron‐rich charge‐plasma regions through work‐function engineering rather than conventional devices. The simulated results show that the positive interface trap charge can increase the electrostatic field and improve the source‐channel band alignment; thus, the band‐to‐band tunneling probability is increased. For D it = +1 × 10 13 cm −2 , the ON‐state current is 1.82 µA (compared to 1.20 µA for the neutral condition), and the average subthreshold swing improves from ~35 to 26 mV/dec. The same positive‐trap condition leads to a peak transconductance of about 165 µS/µm and a cut‐off frequency of about 600 GHz. The gate dielectric study shows that the ON current increases with increasing dielectric constant, giving the highest current of about 1.62 µA among the four dielectrics. All interface‐trap conditions show an average subthreshold swing lower than 40 mV/dec for the proposed TFET.
