The introduction of assembly programming is an important step in the education of computer engineers, as it provides a smooth transition from high level programs, developed in prior courses, to low level programs. This transition aims at improving the understanding of how programs are executed by computers, presenting concepts such as instructions, registers, data representation, execution mode privileges, and external devices. Such concepts are fundamental for later courses in the computer systems field, for instance, computer architecture, operating systems, computer networks, cybersecurity, and compiler design. Given the practical coursework intrinsic to computer systems courses, a platform that enables the development of such activities in a hassle-free manner regarding setup and use, can enrich the learning process of students. In this work, we present a set of teaching materials for assembly programming that consists of an extensible web-based simulator, its manual, and an exercise book. The chosen instruction set architecture (ISA) was RISC-V, as it is an open ISA, has a simple and reduced set of instructions, and has seen rising popularity in both academia and industry. The materials are suitable for either introductory courses with simple assembly programming activities or more advanced courses on the topic that may cover peripheral programming, system calls and interrupt handling.
This paper presents our recent experiences of teaching the "Real-time Embedded Systems Design" course by applying a Real-Time Operating System (RTOS) called Eclipse ThreadX. It transitioned to free, open-source software from Microsoft Azure RTOS in 2023. This paper mainly covers how we adopted ThreadX as a real-world RTOS example in lab sessions, including lab tutorials, programming exercises, lab equipment setup, and course projects. Unlike real-time systems courses for computer science majors, we focus on teaching engineering majors (EE and CE) students the design and application development of real-time embedded systems from the practitioner's point of view. This real-time embedded systems design course is for senior and graduate students majoring in electrical and computer engineering. After completing this course, students are expected to demonstrate the ability to design and develop real-time systems for microcontroller-based embedded applications (i.e., STMicroelectronics IoT Discovery Kit). Project-based learning and hands-on learning are the primary teaching approaches employed in this course. Based on our teaching experiences. ThreadX is an RTOS with rich and unique features and utility tools for teaching real-time systems design and developing cloud-based IoT applications. This paper also summarizes our nearly 10 years of experience in teaching FreeRTOS, another widely used open source RTOS, and compares it with ThreadX. Our latest experiences show that combining Eclipse ThreadX and FreeRTOS can yield synergistic benefits in terms of teaching effectiveness.
Cache coherence is a core topic in a parallel computer architecture course. The choice of protocol and other cache design parameters influences the performance of software that shares data across processors, so an in-depth understanding of them is a must-have. This paper discusses an L1 cache simulator that can simulate both SMP and DSM protocols. Students are given the skeleton of a simulator and an implementation of one or more protocols. They are asked to construct implementations of additional protocols, and then measure their performance on traces from standard benchmark suties. The simulator also offers an interactive mode that reports performance metrics after each individual memory access as the student enters them. This simulator is built in C++ and designed with modularity and extensibility in mind, enabling and encouraging further development to add support for more protocols. The paper describes the structure of the simulator, the coherence protocols that have been implemented, as well as sample assignments.
Understanding how computer programs interact with memory caches is key to optimizing system performance. Our paper introduces the Visual Memory Simulator (VMS), a user-friendly tool that visualizes caches' temporal and spatial utilization. VMS has three components: cache simulator, visualization backend, and GUI. It inputs either a C program or a memory trace. VMS also provides a tracer so users can generate their memory traces. VMS is useful for students to understand cache concepts and researchers to identify memory bottlenecks. VMS provides an intuitive interface where researchers can input code or traces and instantly see cache utilization. Dynamic visualizations help identify optimization possibilities by showing how programs interact with the cache hierarchy. Moreover, VMS allows exploring cache behavior in different settings, giving researchers insight into the effects of various configurations and access patterns.
This paper introduces Ptah, a project-based learning framework for teaching computer architecture by engaging students in designing and deploying NLP-controlled drones powered by edge computing and Kubernetes orchestration. Ptah provides a hands-on educational experience by integrating lightweight NLP models such as BERT into containerized microservices running on modular edge hardware-including Turing Pi 2.5 with Jetson Orin NX, TRK1 with 32 GB RAM, and Turing Pi 2.0 with Jetson Nano and Raspberry Pi Compute Module 4-coordinated via ClusterHAT 2.0 and DeskPi Super6C with Pi Zero 2 W nodes. As students issue spoken commands like "hover," "move forward," or "return home," they witness live end-to-end latencies (1 000-3 000 mu s) as inputs flow through a scalable microservice pipeline orchestrated by K3s and RabbitMQ. Crucially, Ptah exposes L1/L2 cache miss rates and TLB-miss behavior via simple perf and /proc/pid/pagemap experiments on the Orin NX, linking textbook CPU/memory abstractions to real hardware measurements. Learners gain intuitive insights into core architectural concepts-CPU scheduling, I/O systems, memory access, parallelism, and system bottlenecks-through real-time feedback and visualization of how high-level AI-driven commands propagate through hardware and software layers. Deployed in the Reconfigurable Space Computing Lab and integrated into NASA MINDS and DoD-funded studies, Ptah demonstrates a replicable, future-ready model for bridging theory and practice in computer architecture education.
