Discrete Event Simulations (DES) are one of the most widespread approaches to model complex computer systems and are thus crucial for virtual prototyping. In this paper, we consequently propose A RISC-V-Coupled Accelerator for DES (ARCADES). We realize this by leveraging RISC-V extensions to allow for control of the accelerator, as well as implementing our custom event queue and process queue in hardware. We evaluate the accelerator using an FPGA implementation. Our experiments show that in event-heavy scenarios compared to a software implementation, speedups of up to 2.05x can be achieved. Owing to our accelerator being tightly coupled with a PicoRV32 RISC-V processor, we can achieve a high level of configurability and extendability, with ARCADES intended to serve as the base for efficient ASIC DES accelerators.
Systolic arrays are widely used for high-performance digital computations, enabling efficient and parallel execution of operations such as matrix multiplication and convolution. They are deployed in digital signal processing and embedded systems, and they have been more recently adopted to accelerate deep neural networks. However, due to manufacturing defects, aging, and harsh environments, systolic arrays are vulnerable to faults, which can compromise computation reliability. These vulnerabilities call for reliability analysis and hardening methods. Since full triplication induces a high hardware overhead, this work introduces an automatic method that applies redundancy only to the most impactful flip-flops in the processing elements. FPGA simulations show a wide Pareto trade-off between reliability and hardware resources, offering flexible protection levels for fault-resilient systems.
The increasing complexity of cyber-physical systems makes fast simulators essential in the early phases of development. In this paper, a novel approach is proposed to take advantage of a C++-based embedded language (StreamPU) combined with a high speed hardware simulation framework (Verilator). This new methodology is evaluated on three different scenarios featuring control systems. Compared to existing solutions, speed-up factors from x2.25 to more than x3000 are achieved with small error margins. The proposed methodology leverages free and open-source tools, making it easily available to the community. Moreover, this approach can be extended to support hardware-in-the-loop simulations.
Instruction set simulators (ISSs) play an important role in embedded software development. Integrated in virtual platforms, they enable coding, testing, and performance evaluation without the need for physical platforms. However, simulations incur a performance penalty over native execution, resulting in slow simulation speeds for complex applications. We realize that in interpreter-based ISS developers' first choice when detailed processor pipeline and cache simulation are required - the simulator's own instruction fetch and decode stages substantially contribute to overall runtime. We propose a novel simulator instruction fetch and decode cache architecture: (a) We use instruction encodings for cache indexing instead of the program counter, (b) we introduce separate instruction fetch and decode caches instead of a single, unified cache, and (c) we introduce a tiered cache architecture, comprising private and global caches for multicore guest architectures. We have implemented our novel caching schemes in the commercial Synopsys ARC((c)) nSIM ISS that provides an instruction accurate processor model for the Synopsys ARC processor families. We evaluated our new simulator cache architecture using complex real-world workloads and guest configurations with up to 128 simulated guest cores, where we demonstrate average speed-ups of 1.31x over a state-of-the-art baseline scheme, while requiring only 27% of the original cache memory.
The increasing complexity of modern hardware designs necessitates shifting from traditional Register-Transfer Level (RTL) abstractions to higher-level modeling approaches. One of these approaches, the Universal Specification Format (USF), based on metamodeling and embedded in the Python programming language, enables the uniform expression of digital hardware systems’ functional and temporal behavior. While USF models are inherently static, conventional hardware development heavily relies on simulation for tasks ranging from early validation and debugging to dynamic verification and virtual prototyping. Bridging the gap between static specifications and dynamic development needs, we present a novel code generation approach that transforms USF models into executable behavioral models. Our method employs static scheduling with user-defined parallelism, producing executable and synthesizable models for cycle-accurate hardware simulation and emulation. Applying our approach to both the simulation and synthesis of a concrete component specification and variants hereof demonstrates the feasibility and reusability of the proposed code generator.
