Discrete Event Simulations (DES) are one of the most widespread approaches to model complex computer systems and are thus crucial for virtual prototyping. In this paper, we consequently propose A RISC-V-Coupled Accelerator for DES (ARCADES). We realize this by leveraging RISC-V extensions to allow for control of the accelerator, as well as implementing our custom event queue and process queue in hardware. We evaluate the accelerator using an FPGA implementation. Our experiments show that in event-heavy scenarios compared to a software implementation, speedups of up to 2.05x can be achieved. Owing to our accelerator being tightly coupled with a PicoRV32 RISC-V processor, we can achieve a high level of configurability and extendability, with ARCADES intended to serve as the base for efficient ASIC DES accelerators.
Systolic arrays are widely used for high-performance digital computations, enabling efficient and parallel execution of operations such as matrix multiplication and convolution. They are deployed in digital signal processing and embedded systems, and they have been more recently adopted to accelerate deep neural networks. However, due to manufacturing defects, aging, and harsh environments, systolic arrays are vulnerable to faults, which can compromise computation reliability. These vulnerabilities call for reliability analysis and hardening methods. Since full triplication induces a high hardware overhead, this work introduces an automatic method that applies redundancy only to the most impactful flip-flops in the processing elements. FPGA simulations show a wide Pareto trade-off between reliability and hardware resources, offering flexible protection levels for fault-resilient systems.
The increasing complexity of cyber-physical systems makes fast simulators essential in the early phases of development. In this paper, a novel approach is proposed to take advantage of a C++-based embedded language (StreamPU) combined with a high speed hardware simulation framework (Verilator). This new methodology is evaluated on three different scenarios featuring control systems. Compared to existing solutions, speed-up factors from x2.25 to more than x3000 are achieved with small error margins. The proposed methodology leverages free and open-source tools, making it easily available to the community. Moreover, this approach can be extended to support hardware-in-the-loop simulations.
Instruction set simulators (ISSs) play an important role in embedded software development. Integrated in virtual platforms, they enable coding, testing, and performance evaluation without the need for physical platforms. However, simulations incur a performance penalty over native execution, resulting in slow simulation speeds for complex applications. We realize that in interpreter-based ISS developers' first choice when detailed processor pipeline and cache simulation are required - the simulator's own instruction fetch and decode stages substantially contribute to overall runtime. We propose a novel simulator instruction fetch and decode cache architecture: (a) We use instruction encodings for cache indexing instead of the program counter, (b) we introduce separate instruction fetch and decode caches instead of a single, unified cache, and (c) we introduce a tiered cache architecture, comprising private and global caches for multicore guest architectures. We have implemented our novel caching schemes in the commercial Synopsys ARC((c)) nSIM ISS that provides an instruction accurate processor model for the Synopsys ARC processor families. We evaluated our new simulator cache architecture using complex real-world workloads and guest configurations with up to 128 simulated guest cores, where we demonstrate average speed-ups of 1.31x over a state-of-the-art baseline scheme, while requiring only 27% of the original cache memory.
The increasing complexity of modern hardware designs necessitates shifting from traditional Register-Transfer Level (RTL) abstractions to higher-level modeling approaches. One of these approaches, the Universal Specification Format (USF), based on metamodeling and embedded in the Python programming language, enables the uniform expression of digital hardware systems’ functional and temporal behavior. While USF models are inherently static, conventional hardware development heavily relies on simulation for tasks ranging from early validation and debugging to dynamic verification and virtual prototyping. Bridging the gap between static specifications and dynamic development needs, we present a novel code generation approach that transforms USF models into executable behavioral models. Our method employs static scheduling with user-defined parallelism, producing executable and synthesizable models for cycle-accurate hardware simulation and emulation. Applying our approach to both the simulation and synthesis of a concrete component specification and variants hereof demonstrates the feasibility and reusability of the proposed code generator.
Software-based power meters, such as PowerAPI, provide a convenient way to monitor energy consumption in computing infrastructures. However, they often struggle to accurately account for static power consumption—the portion of power that remains constant regardless of system activity. This study aims to address these limitations by developing a robust static power estimation model for multi-core CPUs using offline data from controlled experiments. Our approach utilizes five key processor metrics: temperature, voltage, frequency, activity levels, and Running Average Power Limit (RAPL) measurements. We created a custom stress workload to gather data across diverse conditions, ensuring thorough core-specific activity. To address inaccuracies in thermal sensors, we implemented a temperature correction algorithm, refining raw data to enable analysis of core-specific parameters like frequency, voltage, and activity levels. Results show that the static power of all cores combined contributes as much as 12% of the total CPU package power. This methodology is designed to be reproducible and transparent, contributing to energy efficiency research by addressing the limitations of current software power meters and offering an offline analysis of static power consumption to be later integrated with a dynamic power consumption model.
The increasing usage of Field Programmable Gate Arrays has enabled a large range of applications in hardware acceleration. The introduction of High Level Synthesis (HLS) has significantly simplified development and exploration of complex applications. However, HLS still requires strong hardware knowledge and relies on custom domain specific language. Hence, to ease the design burden, new HLS toolchains have been introduced using more expressive compiler frameworks such as Multi Level Intermediate Representation (MLIR). In this context, we aim to use the Julia programming language as a flexible front-end for HLS framework using MLIR, taking advantage of Julia type system, modular infrastructure, and rich libraries. In this paper, we introduce a new compiler that leverages Julia compiler infrastructure in order to generate MLIR code, facilitating hardware acceleration. The value of this approach has been demonstrated in the context of rapid prototyping and exploration of type spaces for numerical algorithms.
As off-chip memory accesses nowadays dominate the overall power consumption of many compute platforms, accurate DRAM power simulation models are an important tool for system designers. Unfortunately, existing open-source models only support older generations of DRAM standards, while current system designs mainly rely on the newest generation including DDR5, LPDDR5 or HBM3. In addition, the existing models are not directly applicable to the new standards because of the much higher data rates and newly introduced features. This paper presents DRAMPower 5, a completely revised version of the popular DRAMPower simulator, which uses newly developed core and interface power models to support the current generation of DRAM standards. In addition, DRAMPower 5 features a redesigned software architecture that enables both fast and accurate simulation. The tool is open source and available on GitHub.
Instruction Set Simulators (ISSs) are important tools for software engineers that develop cross-system applications. To facilitate seamless interaction between user and ISS, achieving a high simulation performance is key. One of the most challenging simulation aspects is the modeling of Floating Point (FP) vector instructions. Differences among Instruction Set Architectures (ISAs), as well as side effects like FP exception flags, require a significant modeling effort, leading to a reduced simulation performance. Moreover, even state-of-the-art simulators, such as QEMU, use scalar instructions to model vector instructions, which even further hampers the simulator's performance. In this paper, we not only propose new methods for the fast simulation of FP vector instructions, we also show how vector instructions of the host system can be leveraged. To demonstrate the practical benefits of our method, we conducted a RISC-V-on-x64 case study. Compared to QEMU, our approach achieves a speedup of 3.5x for individual instructions. As part of a Virtual Platform (VP) executing vector benchmarks, speedups of up to 24.6% can be attained.
As systems-on-chip (SoCs) scale in complexity, monitoring Intellectual Properties (IPs) such as trace components, performance monitoring units (PMUs), and security-related IPs have an essential role in providing insights on the system real-time behavior, allowing for more efficient debugging, performance analysis, and security assurance. In this work, we present a methodology to rapidly prototype and validate hardware monitoring IPs at the pre-silicon stage, by abstracting the rest of the system. The methodology relies on an instruction set simulator (ISS) to generate trace of executed applications and on tools to simulate these traces on the IPs. We propose a platform incorporating this methodology, called Aspycot. It leverages established projects from the open-source hardware community and is designed to be as modular and straightforward as possible. To illustrate the interest and efficiency of Aspycot, we present a case study related to control-flow monitoring to a single core architecture.
Code coverage analysis has become a standard approach in software development, facilitating the assessment of test suite effectiveness, the identification of under-tested code segments, and the discovery of performance bottlenecks. When code coverage of software for embedded systems needs to be measured, conventional approaches quickly meet their limits. A commonly used approach involves instrumenting the source files with added code that collects and dumps coverage information during runtime. This inserted code usually relies on the existence of an operating and a file system to dump the collected data. These features are not available for bare-metal programs that are executed on embedded systems. To overcome this issue, we present NQC(2), a plugin for QEMU. NQC(2) extracts coverage information from QEMU during runtime and stores them into a file on the host machine. This approach is even compatible with modified QEMU versions and does not require target-software instrumentation. NQC(2) outperforms a comparable approach from Xilinx by up to 8.5 x.
Nowadays, High-Performance Computing (HPC) systems need to deliver computational performance by processing complex applications and workloads at high speeds in parallel. To provide computing power, Multiprocessor System-on-Chip, the main design paradigm, is scaled with advanced technology nodes and even with heterogeneity. These improvements open up more design possibilities, leading to an increase in its complexity. Therefore, chip designers are facing unprecedented challenges to find the best Power, Performance, and Area architectural configurations, inducing a Design Space Exploration problem. This work proposes a complete framework to ease the next generation of HPC processor designs. By combining competitive simulators VPSim and McPAT for a realistic estimation of Key Performance Indicators, with a time-consuming simulation-adapted exploration algorithm such as Bayesian Optimization, we leveraged an Automated Design Space Exploration for efficient HPC processor designs based on ARMv8 architecture. We have also demonstrated the potential of Bayesian Optimization to reach a similar or even larger Pareto front than Genetic Algorithm while being around 2 × to 5 × sample-efficient. Furthermore, the diversity of the obtained Pareto-front enables deep analysis of relevant architectural parameters that significantly impact design performances and thus, empowering architects’ knowledge for further targeted design exploration and design choices.
Hardware specialization is seen as a promising venue for improving computing efficiency, with reconfigurable devices as excellent deployment platforms for application-specific architectures. One approach to hardware specialization is via the popular RISC-V, where Instruction Set Architecture (ISA) extensions for domains such as Edge Artifical Intelligence (AI) are already appearing. However, to use the custom instructions while maintaining a high (e.g., C/C++) abstraction level, the assembler and compiler must be modified. Alternatively, inline assembly can be manually introduced by a software developer with expert knowledge of the hardware modifications in the RISC-V core. In this paper, we consider a RISC-V core with a vectorization and streaming engine to support the Unlimited Vector Extension (UVE), and propose an approach to automatically transform annotated C loops into UVE compatible code, via automatic insertion of inline assembly. We rely on a source-to-source transformation tool, Clava, to perform sophisticated code analysis and transformations via scripts. We use pragmas to identify code sections amenable for vectorization and/or streaming, and use Clava to automatically insert inline UVE instructions, avoiding extensive modifications of existing compiler projects. We produce UVE binaries which are functionally correct, when compared to handwritten versions with inline assembly, and achieve equal and sometimes improved number of executed instructions, for a set of six benchmarks from the Polybench suite. These initial results are evidence towards that this kind of translation is feasible, and we consider that it is possible in future work to target more complex transformations or other ISA extensions, accelerating the adoption of hardware/software co-design flows for generic application cases.
gem5 is a popular architectural simulator, for both academic and industrial researchers. It can be used in two configurations: Full System mode and Syscall Emulation mode. The former requires running a real kernel to achieve realistic results, at the cost of increased user effort. In contrast, the latter emulates operating system functionalities, which improves usability but is more prone to producing less accurate results. Due to the absence of a genuine kernel in Syscall Emulation mode, the simulator model of virtual address translation remains inaccurate. In the current gem5 version (v23.0.1.0), the address translation is performed through the lookup of a flat structure that stores all the virtual-to-physical mappings. However, this approach does not reflect the behaviour of a real multi-level page table, lacking the additional latency associated with page walks. In this paper, we present our implementation of the page walk functionality in Syscall Emulation mode for the RISC-V ISA. We show how our page walker affects the performance of simulated benchmarks and also its sensitivity on the TLB size. Furthermore, we make our work publicly available, inviting fellow researchers to utilize and build upon the model to suit their specific requirements.
Modern compiled software, written in languages such as C, relies on complex compiler infrastructure. However, developing new transformations and improving existing ones can be challenging for researchers and engineers. Often, transformations must be implemented bymodifying the compiler itself, which may not be feasible, for technical or legal reasons. Source-to-source compilers make it possible to directly analyse and transform the original source, making transformations portable across different compilers, and allowing rapid research and prototyping of code transformations. However, this approach has the drawback of exposing the researcher to the full breadth of the source language, which is often more extensive and complex than the IRs used in traditional compilers. In this work, we propose a solution to tame the complexity of the source language and make source-to-source compilers an ergonomic platform for program analysis and transformation. We define a simpler subset of the C language that can implement the same programs with fewer constructs and implement a set of source-to-source transformations that automatically normalise the input source code into equivalent programs expressed in the proposed subset. Finally, we implement a function inlining transformation that targets the subset as a case study. We show that for this case study, the assumptions afforded by using a simpler language subset greatly improves the number of cases the transformation can be applied, increasing the average success rate from 37%, before normalisation, to 97%, after normalisation. We also evaluate the performance of several benchmarks after applying a naive inlining algorithm, and obtained a 12% performance improvement in certain applications, after compiling with the flag O2, both in Clang and GCC, suggesting there is room for exploring source-level transformations as a complement to traditional compilers.
The paper introduces a modeling methodology aimed at thoroughly exploring the design space of multi-die chip architecture tailored for High-Performance Computing (HPC). For accurate simulations, we leverage the capabilities of gem5's Ruby for its robust CPU models and cache coherence protocols, providing a comprehensive representation of die architecture. Die-to-die interfaces are modeled using SystemC TLM, offering flexibility to integrate with other simulators. This enables co-simulation with varying abstraction levels, making it well-suited for the design analysis of multi-die chip architecture. We present, to the best of our knowledge, the first attempt to integrate gem5's Ruby memory system with SystemC TLM for the modeling of multi-die chip architecture. The benefits of this model are demonstrated through the instantiation of a multi-die design using modern Arm architectures with four compute dies and twoexecuting STREAM Triad with Linux, followed by a comparative performance analysis against a monolithic design.
Emulating chip functionality before silicon production is crucial, especially with the increasing prevalence of RISC-V-based designs. FPGAs are promising candidates for such purposes due to their high-speed and reconfigurable architecture. In this paper, we introduce our Makinote, an FPGA-based Cluster platform, hosted at Barcelona Supercomputing Center (BSC-CNS), which is composed of a large number of FPGAs (in total 96 AMD/Xilinx Alveo U55c) to emulate massive size RTL designs (up to 750M ASIC cells)1. In addition, we introduce our FPGA shell as a powerful tool to facilitate the utilization of such a large FPGA cluster with minimal effort needed by the designers. The proposed FPGA shell provides an easy-to-use interface for the RTL developers to rapidly port such design into several FPGAs by automatically connecting to the necessary ports, e.g., PCIe Gen4, DRAM (DDR4 and HBM), ETH10g/100g. Moreover, specific drivers for exploiting RISC-V based architectures are provided within the set of tools associated with the FPGA shell. We release the tool online for further extensions.(2) We validate the efficiency of our hardware platform (i.e., FPGA cluster) and the software tool (i.e., FPGA Shell) by emulating a RISC-V processor and experimenting HPC Challenge application running on 32 FPGAs. Our results demonstrate that the performance improves by 8 times over the single-FPGA case.
When deploying Artificial Neural Networks (ANNs) onto multi-core embedded platforms, an intensive evaluation flow is necessary to find implementations that optimize resource usage, timing and power. ANNs require indeed significant amounts of computational and memory resources to execute, while embedded execution platforms offer limited resources with strict power budget. Concurrent accesses from processors to shared resources on multi-core platforms can lead to bottlenecks with impact on performance and power. Existing approaches show limitations to deliver fast yet accurate evaluation ahead of ANN deployment on the targeted hardware. In this paper, we present a modeling flow for timing and power prediction in early design stage of fully-connected ANNs on multi-core platforms. Our flow offers fast yet accurate predictions with consideration of shared communication resources and scalability in regards of the number of cores used. The flow is evaluated on real measurements for 42 mappings of 3 fully-connected ANNs executed on a clock-gated multi-core platform featuring two different communication modes: polling or interrupt-based. Our modeling flow predicts timing with accuracy and power with accuracy on the tested mappings for an average simulation time of 0.23 s for 100 iterations. We then illustrate the application of our approach for efficient design space exploration of ANN implementations.
Nowadays, DRAM subsystem configuration includes a large number of parameters, resulting in an extensive design space. Setting these parameters is a challenging step in system design as the parameter-workload interactions are complex. Since design space exploration by exhaustive simulation is infeasible due to limited computing resources and development time, semi-automatic configuration involving both manual as well as simulation-based decisions is state-of-the-art. However, it requires a lot of expertise in the DRAM domain as well as application knowledge, and there is no guarantee for a good performance of the resulting subsystem. In this paper, we present a new framework that fully automatizes the DRAM subsystem configuration for a given parameter space and set of target applications. It is based on irace, a software package originally developed for automatic configuration of optimization algorithms. We show that the framework finds nearly-optimal configurations, while only a fraction of all application-configuration combinations has to be evaluated. In addition, all returned configurations perform better than a predefined standard configuration. Thus, our framework enables designers to automatically determine a suitable DRAM subsystem for their platform.
In this paper we present ReDroSe, a heterogeneous compute system based on embedded CPUs, FPGAs and GPUs, which is integrated into an existing UAV platform to allow real time SLAM based on a Truncated Signed Distance Field (TSDF) directly on the drone. The system is fully integrated into the existing infrastructure to allow ground control to manage and monitor the data acquisition process. ReDroSe is evaluated in terms of power consumption and computing capabilities. The results show that the proposed architecture allows computations on the UAV that were previously only possible in post-processing while keeping the power consumption low enough to match the available flight time of the UAV.
