Network-on-Chip (NoC) based architectures are recently proposed to accelerate deep neural networks in specialized hardware. Given that the hardware configuration is fixed post-manufacture, proper task mapping attracts researchers’ interest. We propose a travel time-based task mapping method that allocates uneven counts of tasks across different Processing Elements (PEs). This approach utilizes the travel time recorded in the sampling window and implicitly makes use of static NoC architecture information and dynamic NoC congestion status. Furthermore, we examine the effectiveness of our method under various configurations, including different mapping iterations, flit sizes, and NoC architectures. Our method achieves up to 12.1
This work presents HyRPF, a hybrid approach for simulating RRAM-based memory blocks and registers on FPGAs. HyRPF combines the accuracy and speed of physical prototypes with the scalability and cost-effectiveness of computer simulations. Our approach is implemented in the form of advanced IP blocks, which facilitate rapid prototyping of computer architectures that integrate RRAM memory. These blocks are intended to replace existing memory seamlessly, allowing for quick implementation of system designs and tests while also addressing critical challenges such as functional and non-functional device properties. Statistical models are utilized to account for various temporal and non-temporal variabilities and environmental conditions, including temperature influences. Additionally, energy consumption estimates can be conducted. The performance of our approach is validated by simulating register files and caches within a RISC-V processor architecture. The evaluation shows that HyRPF achieves functional accuracy comparable to purely software-based solutions and faithfully reproduces all essential properties of RRAM devices with minimal resource utilization, while outperforming them in terms of simulation speed and achieving a performance faster than real-time. HyRPF has the potential to significantly accelerate the development and testing of RRAM-based systems, providing researchers and engineers with a versatile and easy-to-use tool that balances accuracy and efficiency.
As power density becomes the main constraint of multicore systems, managing power consumption using DVFS while providing the desired performance becomes increasingly critical. Reinforcement learning (RL) performs significantly better than conventional methods in performance-power optimization under different hardware configurations and varying software applications. RL agents learn through trial-and-error by receiving rewards which is defined by an objective function (e.g. instructions-per-second (IPS)) within specified constraints (e.g. power budget). System and application requirements lead to changing objectives and constraints which in turn result in different reward functions. The RL agents adapt to these changing objectives and constraints (and hence reward functions). Equivalent-policy invariant comparison (EPIC) is a popular technique to evaluate different reward functions. EPIC provides a numerical score which quantifies the difference in two reward functions. In this work, we use this EPIC distance (score) to transfer knowledge and improve learning for changing reward functions. Experimental results using a DVFS enabled RISCV based system-on-chip implemented on an FPGA shows 16.2
The PMDI project aims at radically improving the safety of urban mobility by extending STEP, an automotive data management and analytics platform, to support real-time and near-real-time use cases, particularly focusing on dangerous crossings at urban intersections. Such capabilities will be achieved by deploying STEP on Multi-access Edge Computing (MEC) hardware modules, and integrating within the platform fast AI video and image analytics as well as danger detection algorithms taking as inputs V2X messages from a variety of sources, including (virtual) on-board units and infrastructural sensors. To ensure that dangerous conditions are correctly learnt by AI algorithms, digital twins of the road sections under examination will be built leveraging domain specific language technologies designed to ease the integration.
Large-scale cyber-physical systems, such as those for subway transportation or air traffic control, are becoming increasingly complex and often need to operate without human intervention. At the same time, these systems are subject to high requirements on the timing behavior and fault-tolerance. Consequently, the detection and mitigation of both hard and soft errors is of high importance in the already complex systems design process. The main challenges towards fault-aware real-time systems is the overall system design, in which the sheer size of the state-space and the system's complexity exceeds the capacity of today's development tools. In this paper, we present a new holistic methodology called FAA+RTS, for designing fault-aware adaptive real-time systems. We cover the entire path from system specification using a coordination language, via design-space exploration and task scheduling to the adaptive fault-aware runtime environment. Mitigating both hard and soft errors addresses competing requirements. Improving soft error tolerance (through redundant execution) may accelerate the aging process of silicon, thus expediting hard error failures. FAA+RTS is a novel solution as it integrates previously-isolated methods for dealing with multiple constraints into a single framework, presenting a single overview of all possible trade-offs to the application designer. This integration ensures that all aspects of system design, from specification to execution, are cohesively addressed, resulting in a robust and reliable system. We exemplify FAA+RTS using industrial-sized autonomous subway transportation system as a use-case.
While the potential of in-memory RRAM computation for achieving energy-efficient NNs is recognized, concerns persist about its relative scalability to support modern NNs with billions of parameters. In this context, this paper presents GLoRia, a GPU-RRAM architecture and associated software stack to handle these limitations. We strategically identify the optimal NN layers for RRAM acceleration, enhancing the scalability of RRAMs for complex NN architectures and reducing energy consumption. We validate our approach using practical large CNN and GPT models, showing a 6.4 × decrease in energy consumption, without compromising inference accuracy, thanks to the proposed strategy.
OpenGL SC 2 is Khronos' Graphics API for safety critical systems. However, unlike other Khronos' APIs, available OpenGL SC 2 drivers are only provided by vendors to their customers. This hinders the wide adoption of OpenGL SC 2, which is limited to a niche market, since there are very limited available resources for it. In this work, we describe the design and implementation of an Open Source Installable Client Driver (ICD) and offline compiler on top of OpenGL ES 2.0. Thus, our solution enables the development of OpenGL SC 2.0.1 applications on any embedded system, as well as their deployment on selected safety critical platforms, which do not have an available OpenGL SC 2.0.1 driver yet.
Due to the resource constraints and the increasing environmental impact of embedded systems, the development of frameworks to optimize the footprint of instruction set architectures becomes critical. This paper presents SIZALIZER, a multi-layer analysis framework for the co-design of embedded C/C++ applications and RISC-V instruction set extensions. SIZALIZER embodies a novel approach by automating analysis across three layers: LLVM intermediate representation, executable binary code, and runtime instruction execution using techniques such as data flow graph, static binary, and dynamic execution analysis. The analysis performed with the Embench benchmark demonstrates SIZALIZER's potential to identify optimization opportunities for both static and dynamic code sizes. The framework's unique architecture enables it to distill actionable insights from complex software structures and guide size-optimizing ISA improvements. The proposed improvements result in a calculated static and dynamic improvement of approximately 30 %.
The RISC-V instruction set architecture (ISA) is increasingly gaining traction as an open-source standard, enabling the development of a variety of processor designs. These designs are capable of addressing a broad spectrum of application needs, spanning from embedded systems to high-performance computing. The RISC-V ISA features a modular structure, offering a selection of base ISAs and standardized extensions for customization. In this work, we present the first and open-source extension of a SystemC TLM-based RISC-V Virtual Prototype (VP) which supports the RISC-V “P” Packed-SIMD Version 0.9.11-draft-20211209 called RV-VP ^2 . The RISC-V VP is an open-source simulation platform in SystemC TLM that supports RV32GC and RV64GC. The RISC-V VP is extended for the P-extension of the RISC-V for RV32 specification to focus on simulating embedded application scenarios. A total of 243 instructions are added in the RISC-V VP simulator, which belongs to the mandatory specification of P-extension for RV32. The extended RISC-V VP simulator is evaluated for different test cases; matrix multiplication, convolution, max-pooling, and fully connected layer, to demonstrate the efficiency of P-extension in comparison to base ISA. A convolution neural network called Lenet-5 is also used as a test case to compare performance with the base RV32IM. The results show a maximum speed-up of 5.87 × and 2.97 × when using P-extension for a 4-way (8-bit) SIMD and a 2-way (16-bit) SIMD for matrix multiplication respectively. For Lenet-5 a speed-up of 4.08 × when using P-extension (4-way (8-bit) SIMD) was observed.
To find concurrency bugs in multithreaded software and to be able to reconstruct synchronisation bottlenecks, it is necessary to understand concurrency-related aspects of such programs (shared variables, used synchronisation mechanisms, synchronisation intentions). However, static and dynamic analysis approaches (including the hybrid ones) either overapproximate their results, or are prone to missing some concurrency-related aspects. As a consequence, testers and software architects have to work in the dark when trying to choose tools for finding concurrency bugs and when trying to optimize multithreaded programs to take full advantage of parallel computing potential of multicore processors. To solve this problem, we suggest to divide the activities around synchronisations into two parts. In the first part, developers should only specify high-level intentions regarding access to shared variables. In the second part, it should be possible to automatically transfer these intentions to concrete programming-language specific synchronisation mechanisms. To enable this solution, we have developed the AutoSync framework that provides interfaces for specifying high-level synchronisation intentions and then automatically maps these to optimal synchronisation mechanisms (e.g., locks). AutoSync by design avoids concurrency bugs and is able to provide to architects information about program's concurrency-related aspects so they can perform necessary optimisations.
In the XANDAR project, a holistic model-based toolchain has been formulated that follows the X-by-Construction (XbC) paradigm i.e., a "step-wise refinement from specifications to executable code" that results in systems with guaranteed non-functional properties. XANDAR defined also meta-model extensions, a library of safety, fault-tolerance, and security patterns, and investigated many further techniques for design automation, verification, and validation. In the project, the actual code generation procedure is performed by the XbC backend that efficiently performs the code optimizations, code parallelization, scheduling, mapping, and run-time system generation of the input software modules on the target platform ensuring that the predefined deadlines are met. This paper describes the main features of the XbC backend including the generation of the hypervisor configuration files that are customized for the target multicore platform. The use cases analyzed in XANDAR showcased that the proposed XbC backend was able to output acceptable solutions in an efficient manner.
In many FPGA-based systems, only sequential system control structures modeled by finite state machines are actually required. In order to deal with complexity, design time, and verification issues, which are weaknesses of traditional hardware description languages, it may be preferred to describe the control flow behaviorally in software. However, it is reported that high-level synthesis for FPGA often generates inferior results in terms of resources and performance when translating software-style control flow description to hardware. In this paper, the NanoSoftController is proposed as an open-source soft processor, which is optimized for minimal and efficient logic resource usage on FPGA platforms. It is targeted at processing sequential finite state machine functionality in software, featuring a compact ISA for control flow in embedded systems and a tiny accumulator-based data path. Furthermore, an efficient mapping of memory to small distributed LUT RAM instances enables its use as a system state machine controller in even very resource-constrained FPGA designs, requiring only 104 slice LUTs and 76 slice registers in total. However, despite all optimizations, in a case study with high-level synthesis results of three reference software-style control applications, i.e., electronic door lock, smart glucose sensor, and sequential sensor network node, a better resource efficiency could not be shown. We evaluate the negative results and provide lessons we learned from them.
Digital microfluidic biochips allow the execution of biochemical protocols on a chip-scaled device delivering cost and performance advantages over the traditional benchtop wet-laboratory processes. Several microfluidic high-level programming languages have been proposed, but none is currently adopted as a standard since their compilers and execution engines often target specific platforms. To address this issue and favor standardization, we propose a biochip-independent execution engine and low-level target language. The execution engine supports the execution of parallel synchronized tasks allowing each droplet or process to be controlled by an independent task. The target language run by the engine is inspired by traditional computer instruction set architectures and offers instructions covering the full range of low-level functionalities offered by digital biochips. The versatility of the proposed solution and its ability to support the selection and iteration control structures commonly used in programs is demonstrated with a real-life case study that sorts droplets based on real-time measurements of their color.
The use of IoT systems in industrial environments provides tremendous benefits and economic value leading to an exponential rise in their adoption. Their extended use, however, does not come without concerns related to potential security threats, thereby creating an obstacle in their further use in the field. To address these security concerns, we introduce a specialized Industrial Intrusion Detection System (I2DS). Our proposed system merges the capabilities of deep learning (DL) with FPGA-based hardware acceleration techniques, enabling it to detect subtle anomalies and potential cyber threats that may evade conventional rule-based intrusion detection systems (IDS) in an effective way. More specifically, by implementing the system on FPGA hardware, we achieve low-latency, high-throughput processing of network traffic, essential for real-time intrusion detection in industrial settings. Our architecture is scalable and can be adapted according to network bandwidth requirements, while remaining lightweight, making it an ideal solution for the stringent resource constraints often encountered in IoT environments. The proposed solution has been validated with the modbus TON-IoT dataset, achieving up to two orders of magnitude higher performance compared to a software equivalent implementation.
Digital microfluidic biochips provide a controlled and miniaturized environment to carry out biochemical protocols in an automated fashion. Software-based simulators are essential tools that aid the design of such protocols by enabling users to verify correct execution before targeting the physical biochip. To produce a simulation that is faithful to reality, the fluidic behavior of the droplets and their interaction with the driving electrodes must be taken into account. This paper presents a framework for simulating DMF biochips in a resource-constrained web-based environment. The framework is based on a novel droplet model that uses logic-based calculations to capture fluidic behavior. Thus, enabling to faithfully simulate the movement, merging, and splitting of arbitrary-shaped droplets with a low-computational footprint. The simulation framework also includes modular component models to capture the behavior of sensors and actuators, an event-driven simulation engine, and a graphical user interface. The framework is implemented as a client-side web application and runs in a browser. The evaluation carried out using artificial and real-life test cases shows that the framework can deliver real-time simulations with a high level of fidelity.
The Italian foundation for Security and Rights in Cyberspace (SERICS) is in charge of managing the current, broad range, research in a variety of computer security domains, ranging from strictly computer related aspects, such as OS and Virtualization security, to the development of new cryptographic techniques, up to tackling human, social and legal problems related to computer security and privacy. The SERICS project is founded by the Italian National Recovery and Resilience Plan (NRRP), which in turn receives funding from the EU - NextGenerationEU programme. The SERICS foundation is managing the STRIDE project, to tackle the aforementioned research challenges. In the context of the STRIDE projects, a cascade call was made to tackle specific aspects of the overall reseach challenges. The two-years AQuSDIT project, winner of the aforementioned cascade call, aims to tackle the current open problems in the digital identity realm, with a particular focus on resistance to quantum computer-based attacks, and ledger-based technologies for identification and supply chain tracking. In this context, the research activities at Politecnico di Milano focus on the design of post quantum cryptosystems, and their secure and efficient realization as hardware components, either in the form of full accelerators, or support to existing computing infrastructures. In the following, we will present an overview of the research activities of the 2-year AQuSDIT project, together with an outlook on the first research results which have been obtained by the group of participants from Politecnico di Milano.
Racetrack memory (RTM) is a promising non-volatile memory (NVM) technology that offers exceptional density, power and performance benefits over other NVM and conventional memory technologies. RTM cells have the unique capability of storing hundreds of data bits per cell and are equipped with one or more access ports. However, accessing data in an RTM cell requires the data to be shifted and aligned to an access port, introducing performance and energy overheads and potentially leading to misalignment faults. A misalignment fault occurs when after the shift operation, the desired data is not properly aligned to an access port and incorrect data is read from the RTM cell. Countermeasures have been proposed to mitigate the effects of these faults on applications' accuracy, albeit at the cost of increased overhead. There is potential to balance the trade-offs between acceptable drops in accuracy and enhancements in performance, especially in error-resilient applications such as Binarized Neural Networks (BNNs). However, there exists no tool that enables effective exploration of this design space and assess the potential trade-offs. This paper introduces NetDrift, a framework which facilitates investigation into the impact of RTM misalignment faults on BNNs accuracy at finer granularities. It enables controlled error injection in selected BNN layers with varying fault rates and simulates the impact of accumulated errors in weight tensors of several BNN models (FashionMNIST, CIFAR10, ResNet18) stored in RTM. The framework allows for tuning reliability for performance and vice versa, providing an estimate of the number of inference iterations required for a BNN model to drop below a certain lower threshold, with no protection, limited protection, and full protection, along with the associated impact on performance. The tool is openly available on Github.
Every year, the disparity between processing power and memory bandwidth continues to expand. This well-established trend has been recognized for several years. Recently, innovative concepts have emerged to address and narrow this growing gap. One notable example of such technology is High Bandwidth Memory (HBM), which is specifically designed to tackle this challenge. HBM has a much higher throughput thanks to their wider data buses, making it an innovative solution for this problem. Due to its configurability and timing requirements, HBM and Field-Programmable Gate Arrays (FPGAs) offer a great combination for prototyping, and the hardware that includes both is slowly gaining popularity and accessibility. In this work, we introduce an open-source simulator capable of accurately predicting and modeling HBM based FPGA systems in a fast-prototyping manner. This design not only simulates an HBM but also a memory controller and a memory interconnect, like the one used by AMD/Xilinx. To prove accuracy, this work shows side-by-side comparison between the real hardware and simulated benchmarks of different specific types of memory access patterns, where we measure an overall error of 9.91
Memory corruption bugs remain a significant concern in applications developed using memory-unsafe languages, such as C/C++. Adversaries can exploit these bugs and perform arbitrary read and write operations. These arbitrary reads can target cryptographic keys, severely compromising their secure operation. In this paper, we introduce iVault a lightweight approach to securely store private and secret cryptographic keys. iVault encodes cryptographic keys within the machine instruction immediates and leverage architectural mechanisms to protect the.text segment from being disclosed. We assess iVault in terms of performance and code size expansion, and we show that it represents a viable solution for safeguarding cryptographic keys.
Efficient processing architectures for irregular data patterns require vector element addressing with flexible indices. Therefore, state-of-the-art SIMD vector extensions implement gather and scatter instructions for indexed addressing of data in memory. In vertical vector processors, different data is processed sequentially in parallel lanes and can be exchanged via chaining. This paper proposes an extension of such chaining mechanisms in a vertical vector processor architecture (V2PRO) to flexibly chain not only data but also address offsets between vector lanes. The indirect addressing enables vector access patterns with irregular strides for both register file and memory. The extension has a low hardware overhead of +4.8
