Network-on-Chip (NoC) based architectures are recently proposed to accelerate deep neural networks in specialized hardware. Given that the hardware configuration is fixed post-manufacture, proper task mapping attracts researchers’ interest. We propose a travel time-based task mapping method that allocates uneven counts of tasks across different Processing Elements (PEs). This approach utilizes the travel time recorded in the sampling window and implicitly makes use of static NoC architecture information and dynamic NoC congestion status. Furthermore, we examine the effectiveness of our method under various configurations, including different mapping iterations, flit sizes, and NoC architectures. Our method achieves up to 12.1
This work presents HyRPF, a hybrid approach for simulating RRAM-based memory blocks and registers on FPGAs. HyRPF combines the accuracy and speed of physical prototypes with the scalability and cost-effectiveness of computer simulations. Our approach is implemented in the form of advanced IP blocks, which facilitate rapid prototyping of computer architectures that integrate RRAM memory. These blocks are intended to replace existing memory seamlessly, allowing for quick implementation of system designs and tests while also addressing critical challenges such as functional and non-functional device properties. Statistical models are utilized to account for various temporal and non-temporal variabilities and environmental conditions, including temperature influences. Additionally, energy consumption estimates can be conducted. The performance of our approach is validated by simulating register files and caches within a RISC-V processor architecture. The evaluation shows that HyRPF achieves functional accuracy comparable to purely software-based solutions and faithfully reproduces all essential properties of RRAM devices with minimal resource utilization, while outperforming them in terms of simulation speed and achieving a performance faster than real-time. HyRPF has the potential to significantly accelerate the development and testing of RRAM-based systems, providing researchers and engineers with a versatile and easy-to-use tool that balances accuracy and efficiency.
As power density becomes the main constraint of multicore systems, managing power consumption using DVFS while providing the desired performance becomes increasingly critical. Reinforcement learning (RL) performs significantly better than conventional methods in performance-power optimization under different hardware configurations and varying software applications. RL agents learn through trial-and-error by receiving rewards which is defined by an objective function (e.g. instructions-per-second (IPS)) within specified constraints (e.g. power budget). System and application requirements lead to changing objectives and constraints which in turn result in different reward functions. The RL agents adapt to these changing objectives and constraints (and hence reward functions). Equivalent-policy invariant comparison (EPIC) is a popular technique to evaluate different reward functions. EPIC provides a numerical score which quantifies the difference in two reward functions. In this work, we use this EPIC distance (score) to transfer knowledge and improve learning for changing reward functions. Experimental results using a DVFS enabled RISCV based system-on-chip implemented on an FPGA shows 16.2
The PMDI project aims at radically improving the safety of urban mobility by extending STEP, an automotive data management and analytics platform, to support real-time and near-real-time use cases, particularly focusing on dangerous crossings at urban intersections. Such capabilities will be achieved by deploying STEP on Multi-access Edge Computing (MEC) hardware modules, and integrating within the platform fast AI video and image analytics as well as danger detection algorithms taking as inputs V2X messages from a variety of sources, including (virtual) on-board units and infrastructural sensors. To ensure that dangerous conditions are correctly learnt by AI algorithms, digital twins of the road sections under examination will be built leveraging domain specific language technologies designed to ease the integration.
Large-scale cyber-physical systems, such as those for subway transportation or air traffic control, are becoming increasingly complex and often need to operate without human intervention. At the same time, these systems are subject to high requirements on the timing behavior and fault-tolerance. Consequently, the detection and mitigation of both hard and soft errors is of high importance in the already complex systems design process. The main challenges towards fault-aware real-time systems is the overall system design, in which the sheer size of the state-space and the system's complexity exceeds the capacity of today's development tools. In this paper, we present a new holistic methodology called FAA+RTS, for designing fault-aware adaptive real-time systems. We cover the entire path from system specification using a coordination language, via design-space exploration and task scheduling to the adaptive fault-aware runtime environment. Mitigating both hard and soft errors addresses competing requirements. Improving soft error tolerance (through redundant execution) may accelerate the aging process of silicon, thus expediting hard error failures. FAA+RTS is a novel solution as it integrates previously-isolated methods for dealing with multiple constraints into a single framework, presenting a single overview of all possible trade-offs to the application designer. This integration ensures that all aspects of system design, from specification to execution, are cohesively addressed, resulting in a robust and reliable system. We exemplify FAA+RTS using industrial-sized autonomous subway transportation system as a use-case.
