Traditional computing systems are constrained by the von Neumann architecture, whereas the human brain demonstrates remarkable parallelism and energy efficiency. Here, we present a two-terminal memristor synapse with tunable conductance, enabling selectable performance in weight update behavior, thereby enhancing the network's learning-memorization abilities and dynamic adaptability. We show that devices with tunable conductance reach 98% accuracy in a standard image recognition task, surpassing ideal linear devices and narrowing the gap between neuromorphic and biological neural networks.
With the surge of big data, database systems are increasingly embedded in application backends to enhance user experience and enable deeper analytics. To meet real-time demands, data centers adopt accelerators, yet memory bandwidth has become a key bottleneck as processor speeds outpace memory advancements. This has driven growing interest in near-data computing to alleviate bandwidth limitations and boost performance. We propose LISA-SQL, a low-cost, FPGA-based in-storage accelerator for SQL databases that integrates computation directly within SSDs. We optimize data management and garbage collection through strategic buffer space allocation within the SSD, anticipating data transfers from DRAM, and implement a dynamic buffer caching system that efficiently manages data flow using DRAM mapping and buffer status tables. Our solution also enhances sort and merge join operations by utilizing DRAM and SSD bandwidth with range partitioning to reduce latency. Furthermore, we reduce write amplification via trim commands and precise logical-to-physical mapping, and bypass the conventional Flash Translation Layer through an internal mapping scheme in the accelerator, significantly cutting host-storage communication overhead. Experimental results show that LISA-SQL achieves up to 2.34x speedup over conventional in-storage accelerators, 3.56x over a 128-thread CPU, and reduces garbage collection overhead by up to 2.81x.
Persistent user buffers have the potential to reduce persistence overhead by eliminating unnecessary data copying, making them particularly well-suited for high-persistence scenarios, such as in mobile systems. However, existing persistent user buffers are often inflexible and inefficient due to the need for specific interfaces to update data and frequent persistence operations. This paper introduces FlexPB, a novel approach for achieving both flexibility and efficiency in persistent user buffers. FlexPB introduces the concept of file-based persistent buffers, significantly improving their usability and adaptability. By leveraging fsync-based persistence semantics, FlexPB ensures efficient and practical data consistency. To further optimize performance, FlexPB dynamically decides whether to incorporate DRAM based on the characteristics of different NVMs and usage scenarios. Experimental results and a case study using SQLite demonstrate substantial performance improvements over traditional approaches, highlighting the effectiveness and practical advantages of FlexPB.
Quad-Level Cell (QLC) flash technology is increasingly adopted in consumer-grade storage systems due to its high density and cost efficiency. However, its inherent two-step programming process and lack of power-loss protection necessitate routing writes through a Single-Level Cell (SLC) cache to ensure data integrity. Under the Zoned UFS protocol, the SLC cache suffers from mismatched management granularity, leading to an enlarged mapping table, inefficient space reclamation, and migration conflicts. To address these issues, we propose ZoneFit, a zoned SLC-QLC co-management framework that incorporates zone-level SLC capacity allocation and zone-level SLC migration. Evaluations on a consumer-grade zoned storage emulator demonstrate that ZoneFit significantly enhances read performance and prolongs the lifespan of flash storage.
Large language models (LLMs) have revolutionized natural language processing, enabling breakthroughs in applications ranging from machine translation to conversational artificial intelligence. However, fine-tuning these massive models presents significant memory challenges, especially when fine-tuning with mixed precision (FP16/FP32) to maintain efficiency and accuracy. Although existing techniques, such as the DeepSpeed fine-tuning framework, can reduce the overhead of host memory using group fine-tuning, these methods suffer from inefficient overflow detection and redundant gradient storage, greatly increasing memory requirements. These drawbacks limit the fine-tuning of large models on memory-constrained devices. To address these challenges, this paper proposes an instant gradient offloading strategy, a fine-tuning approach that significantly reduces memory overhead while maintaining fine-tuning accuracy and speed. Our solution introduces three key innovations: (1) On-the-fly overflow detection: calculated gradients are checked immediately instead of batch checking, eliminating peak memory spikes; (2) Instant gradient offloading: the gradient is offloaded to SSD and loaded when needed, minimizing CPU memory usage; (3) FP16-centric gradient offloading: the type conversion operation of the gradient data is delayed so that it uses FP16 format for data exchange with SSD. Experiments show that the proposed design reduces memory consumption by 77.8% - 85.3% compared to the DeepSpeed offload baseline while maintaining a comparable fine-tuning speed. Specifically, the proposed system can use 128GB of CPU memory to fine-tune a 98B parameter model. These advances make large-scale LLM fine-tuning possible on resource-constrained hardware.
