Network-on-chip (NoC) is currently the chosen paradigm for interconnection in multicore architectures. On the other hand, the development of these architectures with thousands of cores leads to several issues regarding latency and power consumption, especially with conventional wired interconnects. Moreover, they do not support specific features like broadcast and multicast. Radio-Frequency NoC based on OFDMA seems an appropriate solution to overcome such issues, providing low latency for long communications and a significant communication bandwidth with a high spectral efficiency. It also permits a dynamic allocation of the available bandwidth among the different elements of the NoC, according to the communication needs. The routing algorithm has a significant impact on the overall performance of a RF-NoC, by diffusing the traffic in a suitable way between the wired and the wireless paths in order to improve the throughput and reduce the latency. In this paper, a threshold-based routing algorithm is proposed and evaluated for a 32×32 RF-NoC OFDMA architecture with 32 concurrent wireless channels. We demonstrate the importance to finely tune the threshold parameter to achieve a certain level of performance. Simulation results show a significant improvement in terms of latency and throughput.
Energy-efficiency has been a major challenge in compute systems over the last decade. Both embedded and highperformance computing domains are concerned. Many efforts have been currently spent to devise solutions that are capable of providing systems with the best compromises in terms of performance and power consumption. In this paper, we propose an approach for on-line energy-efficiency analysis when executing OpenMP workloads on multicore systems. The novelty of our approach lies in the ability to monitor energy efficiency at runtime without prior knowledge of the application profile or code annotation. The solution relies on two new metrics: the Chunks per Second (CpS) and Chunks per Joule (CpJ). The former captures the quantity of work achieved by threads per unit time (i.e. a performance indicator). The latter indicates the quantity of work achieved by threads per unit energy, also corresponding to the performance per watt (i.e. an energy efficiency indicator). As most programs are made of several phases performing different computations for which CpS and CpJ cannot be related, it is crucial to be capable of detecting phase changes such as to perform intra-phase energy efficiency optimizations. For that purpose we devise a specific neural network model derived from the popular auto-encoder largely explored in the machine learning community, that is capable of understanding application profile and track phase changes at run-time. We show that these new metrics allow to perform energy efficiency optimization, and illustrate our approach on the analysis of the SRAD application from the Rodinia benchmark. The energy-efficiency profile analysis of the application is conducted on both an Intel and ARM platforms, showing its flexibility.
With the growing number of cores per processor, on-chip communications are becoming a critical issue. Conventional wired mesh Networks-on-Chips (NoC) are reaching their scalability limit, paving the way for new interconnect technologies such as Radio Frequency (RF), Optics and 3D. This paper presents a new routing mechanism based on the WiNoCoD architecture, a hierarchical RF interconnect with dynamic bandwidth allocation for Chip Multi Processors (CMP). WiNoCoD consists of three levels of hierarchy with an RF NoC at the highest level, a wired mesh NoC and a crossbar at the lowest level. In this paper, we propose a new organisation for the manycore supporting the RF-NoC, and introduce a new routing algorithm that can choose between wired and RF networks in order to optimize the use of RF. We show that the new architecture improves performance in terms of latency and saturation. Platform simulations show a latency reduction for lower transaction rates of up to 10% compared to the original WiNoCoD architecture and up to 30% compared to a wired mesh NoC. Furthermore, smart routing pushes back the saturation threshold up to 20%.
In NoC-based multi-core systems, the communication subsystem accounts for a significant fraction of the energy consumption. Traditional NoCs guarantee error-free data transfer at the expenses of limiting the hardware optimization possibilities. However, in various applications, such as multimedia processing and machine learning, inaccurate outputs within an acceptable variance is tolerable. Recently, approximate NOCs have been proposed as a viable solution to exploit the trade off between the energy efficiency with data approximation. In this context, we propose two coding techniques. First, a combined memory-less integer-value encoding is proposed to reduce the integer-value deviation in the body flit of the approximate NOCs; and second, a crosstalk avoidance code (CAC) to guarantees the exact transmission of the head flit. Our technique improves the energy consumption of the approximate NOCs remarkably and does not introduces any performance or area penalty. Experimental results using a 65nm commercial technology asses the advantages of the proposed coding approach versus conventional transmission. proposed coding in real scenarios.
The use of accelerator-centric processing architectures in different application scenarios, ranging from the cloud to the edge, is nowadays a reality. However, the always increasing stringent operating conditions and requirements continues to push the research around hardware-based processing architectures, which are able to provide medium to high computing performance capabilities while at the same time supporting energy-efficient execution. In addition, reconfigurable devices (i.e., FPGAs) provide another degree of freedom by enabling software-like flexibility by time-multiplexing the computing resources. Nevertheless, bus-based computing platforms still face architectural bottlenecks when data transfers are not handled efficiently. In this paper, the communication overhead in a re configurable multi-accelerator architecture for high-performance embedded computing is analyzed and modeled. The obtained models are then used to predict the acceleration perfomance and to evaluate two different patterns for data transfers: on the one hand, a basic approach in which data preparation and DMA transfers are executed sequentially; on the other hand, a pipelined approach in which data preparation and DMA transfers are executed in parallel. The evaluation method is based on well-known accelerator benchmarks from the MachSuite suite. Experimental results show that using a pipelined data management approach increases performance up to 2.6x when compared to the sequential alternative, and up to 26.46x when compared with a bare-metal execution of the accelerators (i.e., without using the reconfigurable multi-accelerator processing architecture nor an Operating System).
