Speculative execution attacks, such as Spectre Variant 1, leak sensitive data through transient microarchitectural effects. This paper presents a machine learning-based framework for analyzing and mitigating speculative execution vulnerability patterns in RISC-V systems. We extract branch, cache, and timing features from gem5 simulations and validate leakage behavior on a SiFive HiFive Premier P550 platform. Supervised models achieve up to 97.1% accuracy in distinguishing benign and speculative-leak execution windows, while unsupervised methods (K-means, HDBSCAN, and Isolation Forest) independently reveal structural and anomaly-based separation. Feature analysis shows that speculative loads and memory latency are the strongest leakage indicators. We further propose lightweight RISC-V assembly wrappers based on index masking and fence instructions. Results demonstrate that these wrappers shift vulnerable execution toward benign microarchitectural behavior. The proposed approach combines simulation, hardware validation, and learning-based analysis for practical speculative vulnerability analysis and mitigation in RISC-V processors.

The open-source RISC-V Instruction Set Architecture (ISA) is being adopted rapidly in security-sensitive areas such as IoT, edge computing, and aerospace systems, which makes early-stage security validation increasingly important. Yet most existing approaches still depend either on post-silicon testing or on high-level emulation. Neither is well suited to exposing ISA-specific vulnerabilities or microarchitectural side effects during the design phase. As a result, there remains a gap between highlevel security policies and the way hardware actually behaves at runtime, and that gap can leave processors exposed to privilege escalation, memory protection failures, and side-channel leakage that may only become visible late in development. In this paper, we present RV-Sec5, a systematic and policy-driven framework for ISA-level security evaluation built on the gem5 cycle-accurate simulator. RV-Sec5 provides a formal method for translating high-level security invariants, including privilege isolation, Physical Memory Protection (PMP) enforcement, and Control and Status Register (CSR) integrity, into automated cycle-accurate instrumentation points embedded directly in the ISA decoder. By recording precise architectural execution context at instruction commit time, the framework supports specification-driven methodology of privilege escalation attempts and enables systematic correlation between ISA-level events and microarchitectural behavior, including TLB activity and cache state changes, without interfering with functional execution. Our results shows that RV-Sec5 can significantly detects the specification violation on the events that are permitted in User mode, the results shows that after extending the gem5 with the hooks added and ISA modified, it create an overhead on the simulation. The overall overhead of RV-Sec5 for the simulation time is less than 4% and the overhead for the memory usage is less than 2% across the evaluated workloads. RV-Sec5 is a modular, cycle-accurate observation and post-execution detection virtual platform that reduces the gap between architectural security requirements and their enforcement at the Microarchitectural level, using post-silicon testing within the RISC-V processor design flow.

The FLASH interface is a crucial component in modern Microcontrollers (MCUs), serving as an intermediary for transferring instructions between the processor and program memory. Previous studies have demonstrated the effectiveness of Electromagnetic Fault Injection (EMFI) and Laser Fault Injection (LFI) in disrupting the operation of FLASH accelerators, leading to instruction line replay and skip faults. However these studies are limited to the case of sequential code and to a single FLASH interface configuration of the target MCU. In this work, we present an investigation on the impact of Body Bias Injection (BBI) on the FLASH accelerator in a 32-bit MCU.The experiments confirm that BBI can similarly induce instruction line replay and skip faults. A detailed analysis of the fault manifestations under various operational configurations of the FLASH accelerator is provided. The study has also extended the fault model to the case of branch operation (non-sequential code).This research contributes a refined understanding of FLASH interface fault behavior under BBI, and highlights the security implication of the decorrelated design between the Program Counter and the FLASH interface.

The modularity of the RISC-V Instruction Set Architecture (ISA) has accelerated its adoption in security-critical domains, yet it introduces significant challenges for pre-silicon security validation. Current evaluation methods often rely on high-level emulation that overlooks microarchitectural side effects or post-silicon testing that identifies vulnerabilities too late in the design cycle. This paper presents RV-Sec5, a systematic framework for ISA-level security evaluation that leverages the gem5 simulator. Unlike standard simulators, RV-Sec5 introduces a methodology to map high-level security invariants-such as privilege isolation and memory protection-directly to automated, cycle-accurate instrumentation points within the ISA decoder. This approach bridges the semantic gap between abstract security policies and low-level hardware execution. We demonstrate the framework's efficacy through a case study involving unauthorized Control and Status Register (CSR) modifications, showing how RV-Sec5 detects privilege escalation attempts and monitors microarchitectural anomalies, such as TLB flushes and cache state changes, in real-time.

Hash functions are fundamental for ensuring authenticity and integrity in digital communications. Their importance has grown with the advent of Post-Quantum Cryptography (PQC), as many newly standardized PQC algorithms, such as ML-KEM, heavily rely on hash functions for pseudo-random number generation. Among available standards, SHA-3, published by NIST in 2015, is the recommended choice for PQC applications. However, its adoption in embedded platforms remains limited, particularly in the presence of security threats such as side-channel attacks (SCAs). To mitigate SCAs, masking techniques are widely employed, but their implementation on SHA-3 accelerators is complex due to the non-linearity of the Keccak function. Domain-Oriented Masking (DOM) provides strong security guarantees but requires a significant amount of randomness, introducing additional implementation costs often overlooked in the literature. For instance, existing DOM implementations of Keccak demand 1600 bits of fresh randomness per clock cycle, raising practical concerns about randomness generation and deployment overhead. In this work, we present a hardware accelerator supporting all the SHA-3 functions with first-order masking countermeasure based on a DOM implementation of the Keccak core. For the generation of the randomness required by the DOM countermeasure, we implemented a randomness dispatcher based on Trivium and Bivium ciphers, and we evaluated the cost in terms of area of the circuit in FPGA and ASIC of the countermeasure and of the randomness generation. In addition, we assess its security through Test Vector Leakage Assessment on FPGA. Finally, the accelerator is integrated into a RISC-V-based 32-bit SoC and used to accelerate a first-order masked implementation of ML-KEM, achieving a speed-up ranging from 95x to 264x for the SHA-3-based functions of the KEM decapsulation.

Program flow attacks involve disrupting the flow of instruction execution in microcontrollers (MCUs), thereby threatening their operation. While traditional studies focus on program counter or instruction corruptions within pipelines, little attention has been paid to the stages between FLASH memory and the CPU, such as memory accelerators. Body Bias Injection (BBI) is a fault injection technique in which a voltage pulse is applied to the backside of an integrated circuit, i.e. its substrate, causing localized disruptions in the power network. Despite its proven effectiveness in inducing transient faults, to the best of our knowledge, there is no information on its impact on MCU program flow. Within this context, this paper demonstrates that BBI can efficiently disrupt MCU program flow, causing entire instruction lines to be skipped or repeated. It also shows that the most sensitive part of the MCUs against BBI is likely to be the memory accelerator rather than the processor itself.

The rapid proliferation of Internet of Things (IoT) devices imposes stringent demands on energy efficiency, real-time responsiveness, and security, which traditional simulation approaches often fail to address due to their limited ability to capture microarchitectural interactions. This paper introduces Gem5-ML, a gem5-based framework extended with IoT-specific processor, memory, and peripheral models, coupled with machine learning (ML) to accelerate design-space exploration. Representative workloads including sensing, control, communication, and lightweight security kernels are executed in SE mode to collect fine-grained microarchitectural statistics such as cache activity, bus contention, interrupt latency, and execution cycles. These features are used to train surrogate ML models that enable fast and accurate prediction of performance and energy trade-offs, reducing exploration time by up to 10× while maintaining over 90% Pareto front coverage. The framework also incorporates anomaly detection mechanisms capable of identifying reliability issues such as interrupt storms, cache thrashing, and voltage droop with high accuracy. Experimental results demonstrate that Gem5-ML achieves efficient exploration, robust prediction, and actionable insights for energy-aware and secure IoT microcontroller design, highlighting its potential as a scalable methodology for next-generation low-power and resilient embedded systems.

Modern processors employ performance-enhancing features such as speculative execution and multi-level caching, but these same mechanisms can inadvertently expose sensitive information through microarchitectural side channels. This work introduces a precise, simulation-driven framework for identifying how individual cryptographic instructions contribute to such leakage. We present a systematic opcode-level analysis of AES-NI instructions (including AESENC, AESDEC, and AESKEY-GENASSIST) and quantify their susceptibility to Flush+Reload attacks using cycle-accurate gem5 simulations. Our results reveal distinct microarchitectural footprints for each opcode: AES-ENC exhibits measurable timing and cache activity arising from state and round-key memory operations surrounding the hardware-implemented transform, while AESKEYGENASSIST incurs the highest latency due to iterative key-schedule computations. Control-flow instructions such as JNE further amplify leakage by introducing branch mispredictions. A key outcome of this study is the close match between simulation and physical measurements achieving 89% key recovery in gem5 versus 96% on an Intel CPU, demonstrating that gem5 reliably captures the dominant leakage behaviors despite abstracted hardware details. We additionally show that smaller last-level caches intensify leakage by concentrating access patterns, whereas larger caches reduce, but do not eliminate the exposure. Overall, this work provides actionable insights for designing hardened cryptographic software and developing future detection mechanisms, and highlights the value of architectural simulation for early-stage security assessment.

The diversity of Instruction Set Architectures (ISAs), each with its unique constraints and optimization strategies, presents significant opportunities and challenges in processor design. Modern processor vendors exploit these ISAs to enhance security, reliability, and performance. Recent security vulnerabilities, notably Spectre and Meltdown, have highlighted the critical need for robust hardware security measures. In this paper, we employ gem5, a state-of-the-art cycle-accurate simulation tool, to simulate the Spectre attack. We developed and modified scripts for both x86 and ARM architectures to ensure compatibility with gem5 version 23.1. Our simulation setup involved running attack scenarios under various configurations to gather comprehensive data on cache misses, cache hits, mispredicted branches, and level 2 cache hits and misses. In the simulation, we analyzed the trace files generated by gem5, utilizing a range of debug flags such as Exec for disassembly (dasm) insights. By detailed analysis of cache and branch prediction using detailed debug data revealed by gem5 traces, we identify some specific attack patterns that are useful for automating the detection of the attacks. Our future work aims to expand this analysis to include additional attack vectors and find more attack patterns, thereby strengthening our attack pattern recognition capabilities.

Modern computer memories have shown to have reliability issues. The main memory is the target of a security threat called Rowhammer, which causes bit flips in adjacent victim cells of aggressor rows. Numerous countermeasures have been proposed, some of the most efficient ones relying on row access counters, with different techniques to reduce the impact on performance, energy consumption and silicon area. In these proposals, the number of counters is calculated using the maximum number of row activations that can be issued to the protected bank. As reducing the number of counters results in lower silicon area and energy overheads, this can have a direct impact on the production and usage costs. In this work, we demonstrate that two of the most efficient countermeasures can have their silicon area overhead reduced by approximately 50% without impacting the protection level by changing their counting granularity.

Dans un monde de plus en plus digitalisé, le nombre d’objets connectés ne cesse de croitre. Afin d’assurer la sécurité de ce type d’objets, il est nécessaire d’en maitriser la sécurité tant au niveau matériel que logiciel. L’objectif de ce papier est de présenter une formation dispensée par le pôle CNFM de Montpellier. Ce diplôme d’établissement de niveau BAC+6 spécialisé en sécurité des systèmes embarqués allie à la fois cours théorique, mise en pratique à l’Université mais aussi en entreprise.

Due to the globalization of the semiconductor industry, Integrated Circuits (ICs) and Intellectual Properties (IPs) are susceptible to specific threats. IP piracy, overproduction, and introduction of hardware Trojans can indeed compromise valuable design information and trust in the design flow. Logic Locking (LL) is one of the most popular Design-for-Trust techniques that aims to thwart these threats because of the wide range of risks it can prevent. This approach evolves from year to year in order to make it resistant to ever more advanced attacks. While most advanced LL solutions are assumed to be resistant against differential power analysis (DPA), we propose a new attack framework for challenging these approaches and show on several benchmarks that it is possible to reveal more than 88% of the key bits used for locking the designs thanks to DPA.

In today's digital landscape, cryptography plays a vital role in ensuring communication security through encryption and authentication algorithms. While traditional cryptographic methods rely on hard mathematical problems for security, the rise of quantum computing threatens their effectiveness. Post-Quantum Cryptography (PQC) algorithms, like CRYSTALS-Kyber, aim to withstand quantum attacks. Recently standardized, CRYSTALS-Kyber is a lattice-based algorithm designed to resist quantum attacks. However, its implementation faces computational challenges, particularly with Keccak-based functions, which are crucial for security and upon which the FIPS 202 standard is based. Our paper addresses this technological challenge by designing a FIPS 202 hardware accelerator to enhance CRYSTALS-Kyber efficiency and security. We chose to implement the entire FIPS 202 standard in hardware in order to widen the applicability of the accelerator to all possible algorithms that rely on such hash functions, taking care to provide realistic assumptions on system-level integration inside a System-on-Chip (SoC). We provide results in terms of area, frequency, and clock cycles for both ASIC and FPGA targets. An area reduction of up to 22.3% is achieved with respect to state-of-the-art solutions. In addition, we integrated the accelerator inside a 32-bit RISC-V based security-oriented SoC, where we show a strong performance gain on CRYSTALS-Kyber execution. The design presented in this paper performs better in all Kyber1024 primitives, with an improvement up to 3.21x in Kyber-KeyGen.

Post-quantum cryptography represents a category of cryptosystems resistant to quantum algorithms. Such schemes are under the scrutiny of their mathematical security in the context of the NIST standardization process, but they are not side-channel secure at the algorithm level. That is why their side-channel vulnerabilities must be assessed by the research community. In this paper, we present a non-profiled correlation electromagnetic analysis against an FPGA implementation of the standard key-encapsulation mechanism, CRYSTALS-Kyber. The attack correlates an electromagnetic radiation model of the polynomial multiplication execution with the captured traces. With 166,620 traces, this attack correctly recovers 100% of the subkeys. Furthermore, a countermeasure is presented for securing the target implementation against the presented attack.

TSX Asynchronous Abort (TAA) vulnerability is a class of Side-Channel Attack (SCA) that allows an application to leak data from internal CPU buffers through asynchronous Transactional Synchronization Extension (TSX) aborts that are exploited by the recent Microarchitectural Data Sampling (MDS) attacks. Cross-core TAA attacks can be prevented through microcode updates where CPU buffers are flushed during Operating System (OS) context switching, but there is no solution to our knowledge that exists for hyper-threaded TAA attacks in which the attacker leaks data from sibling hardware threads through asynchronous abort. In this work, we have proposed Diminisher, a Linux kernel-based detection and mitigation solution for both hyper-threaded and cross-core TAA attacks. Diminisher can be logically divided into three phases, i.e., scheduling, detection, and mitigation. Diminisher is a lightweight tool to prevent TAA vulnerability. The novelty lies in the methodology that we propose enabling easy extensions to cover other hyper-threaded attacks for which no satisfactory solutions exist yet. Diminisher detects and mitigates the TAA attacks around 99% of the time at a low-performance overhead of 2.5%.

The processors (CPUs) embedded in System on Chip (SoC) have to face recent attacks taking advantage of vulnerabilities/features in their microarchitectures to retrieve secret information. Indeed, the increase in complexity of modern CPU and SoC is mainly driven by the seek of performance rather than security. Even if efforts like isolation techniques have been taken to thwart cyberattacks, most microarchitectural features can open the door to security holes. One typical example is the exploitation of cache memory which keeps track of the program execution and paves the way to side-channel (SCA) analysis and transient execution attacks like Meltdown and Spectre, which take advantage of speculative execution. This paper introduces an ongoing study aiming at analyzing the attacks relying on the hardware vulnerabilities of the microarchitectures of CPUs and SoCs. The main objective is to create a virtual and open platform that simulates the behavior of microarchitectural features and their interactions with the peripherals, like accelerators and memories in emerging technologies. The gem5 simulator, whose configuration can be customized to a specific CPU or SoC architecture, is the basis of our chosen platform for security analysis.

HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L’archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires publics ou privés. Deliverable D3.2 Evaluation of selected memory and communication technologies and exploitation opportunities in compilation and runtime management Florent Bruguier, Thibaud Delobelle, Charles Emmanuel Effiong, Abdoulaye Gamatié, Pierre-yves Péneau, Gilles Sassatelli, Sophiane Senni, Lionel Torres, Erven Rohou