In this work, we present a method to derive the phase jitter (PJ) of PCI Express (PCIe) Gen3 by analyzing both random jitter (RJ) and deterministic jitter (DJ) induced by power noise in a clock network. In the previous jitter analysis methods, the impact of power noise has not been considered when analyzing the jitter of PCIe Gen3 reference clock networks. We apply the proposed method to analyze and validate the main noise sources of PCIe Gen3 PJ violations observed in a system-on-chip (SoC) design implemented at Samsung's 4-nanometer process node. Through various experiments, we found that the main cause of the violation is jitter due to power noise below 50 MHz. By modifying the power management integrated circuit (PMIC) to reduce the low-frequency noise at the PMIC output, we observed a 50% reduction in jitter in the clock network.
Power Distribution Networks (PDNs) in high-speed applications are very important for proper functioning of the IC's. In this paper, the impact of VRM, PCB, IC package and DIE parasitic on PDN is analyzed and how to optimize the PCB in order to achieve the target impedance for high current requirements. The holistic signal integrity approach of considering the coupling of DDR power noise on the parallel interface, affecting the timing and eye quality is studied.
This paper presents a calibration kit designed for a double-ridged waveguide. This custom designed double-ridged waveguide was developed to address the 5G-FR2 standard frequency band of 24 to 53 GHz. It is used as a blindmating interconnect in over-the-air high-volume manufacturing testing of antenna in package devices for 5G-FR2 applications. A TRL calibration kit design is presented together with the measured results obtained with a manufactured prototype of the calibration kit.
The λ/4 resonance due to unwanted stub effect along the signal path can play a significant role for the Chip-to-Module interface running at 224 Gbps in PAM4 which involves a typical optical module connector. A OSFP connector example is considered in this paper and the impact of the residual stub given by the spring wipe is analyzed. The stub resonance is predicted analytically with acceptable error, and the stub notch resonance is extracted from full-wave simulations for several cases of wipe length. A length limit is derived in order to keep the notch frequency of the resonating stub outside the usable bandwidth practically set at 0.75 times the baud rate for the PAM 4 type of modulation.
The inclusion of a receiver decision feedback equalizer (DFE) to Double Data Rate 5(DDRS) synchronous dynamic random access memory (SDRAM)s has increased the complexity of signal integrity (SI) simulation compared to previous DDR technologies. In response, the I/O Buffer Information Specification (IBIS) version 7.1 enables an IBIS algorithmic modeling interface (IBIS-AMI) receiver model to accept an external clock signal. A novel simulation flow is developed which accounts for both DQ (data) signals and their associated DQS (clock/strobe) signal in the evaluation of DDR5 data write and read operations. The effects of including DQS into SI simulation of DDR5 systems are discussed by examining the resulting eye diagrams. It is observed that for system timing margins, the SI quality of the strobe signal becomes just as important as the data signals.
