A Critical Examination of the TCAD Modeling of Hot Carrier Degradation for LDMOS Transistors

LDMOS is one of the most widely used power transistors and has a variety of applications across multiple sectors (automobile, photovoltaics, communication, etc.). Unfortunately, the high applied bias makes Hot Carrier Degradation (HCD) a persistent reliability concern for LDMOS transistors. HCD occurs due to the generation of interface defects (NIT) by energetic electrons/holes, and the degradation rate depends sensitively on gate/drain voltages, doping, and transistor geometry. Several efforts have been made to model HCD in TCAD to predict the HCD susceptibility of next-generation LDMOS transistors. However, the lack of characterization techniques to extract NIT(x) in LDMOS makes it difficult to cross-check ΔNIT(x) obtained from the TCAD models, thereby making reliability aware predictive design difficult. In this paper, we: (a) determine the physical mechanism of HCD in a planar LDMOS using TCAD; (b) demonstrate the capability of the Super Single Pulse Charge Pumping (S2PCP) technique to extract NIT(x) at various points in the LDMOS, (c) quantify the spatial and temporal evolution of NIT(x,t), and compare the experimental results with TCAD predictions; (d) identify the key differences between the experimental and TCAD approach and suggest possible physical mechanisms responsible. This analysis establishes the robustness and identifies the limitations of TCAD modeling of HCD in LDMOS devices.