This paper investigates the impact of titanium (Ti) doping on zinc oxide (ZnO) nano wires (NWs) in non-volatile capacitive memory devices (NVCMDs) through fabrication and characterizations. ZnO NWs were fabricated using pulsed laser deposition (PLD), while Ti thin film (TF) was deposited via electron beam evaporation (ebeam). Field emission gun scanning electron microscopy (FEGSEM) confirmed the formation of ZnO NWs and Tidoped ZnO NWs (Ti:ZnO NWs) on an n-type silicon (Si) substrates, with elemental compositions determined by energy dispersive X-ray spectroscopy (EDX). Structural characterization was conducted on the samples using high-resolution X-ray diffraction (HRXRD). Gold (Au) interdigitated electrodes (IDE) were employed to fabricate two distinct devices: Au IDE/ZnO NWs and Au IDE/Ti:ZnO NWs. Comparative analysis revealed that the Au IDE/ Ti:ZnO NWs device exhibited a lower frequency dispersion (fd) value (0.025x10-9 F) compared to Au IDE/ZnO NWs device (0.029x10-9 F), indicating enhanced signal propagation due to Ti doping. The Au IDE/Ti:ZnO NWs device also demonstrated a high free charge carrier donor concentration (ND) value of 2.02x1012 /cm3, a significant trap concentration (Nt) value of 4.44x1011 /cm3 at an 8 MHz frequency response. Additionally, it exhibited lower tangent loss (tan(delta)) value of 7430, maximum conductance (Gmmax) value of 13.40 mS, lower interface trap state density (ITSD) value of 2.05x10-14 eV-1 cm-2, a maximum memory window (Delta VMW) of 6.9 V at +/- 15 V, improved endurance, and superior data retention, making the Au IDE/Ti:ZnO NWs device a promising candidate for next-generation NVCMDs applications.

Lateral double diffused MOS (LDMOS) transistors have found numerous applications as radio-frequency and power amplifiers in a variety of systems, including satellite communications and high-energy physics experiments. While the LDMOS transistors used in these systems have inherent reliability issues, such as hot carrier degradation (HCD), they are simultaneously subjected to high radiation. Therefore, it is essential to understand how the interface traps created during radiation interact with those created during the HCD stress of these transistors. In this article, we: 1) subject the LDMOS transistors to various total ionizing doses (TIDs) of gamma radiation and HCD stress; 2) use the super single-pulse charge pumping (CP) technique to quantify the generation of interface traps (Delta(NIT)) and trapped charges (Delta(NOT)); 3) study the combined effect of HCD and TID in terms of threshold voltage shift (Delta V-TH) and linear drain current degradation (Delta(ID,lin)); 4) describe the correlation between HCD and TID using well-known physics-based models; and 5) compare our findings with that of an LDMOS of varied geometry, dimension, and bias, illustrating that the model and inferences drawn from the conclusions of this article can be applied to other LDMOS devices as well. This article establishes that the physics of HCD is universal and takes us a step closer to a generalized HCD model for power FETs.

Over the past few decades, power electronics devices have found numerous applications, including high energy physics, drones, space electronics, etc. It is well-known that the devices used in these applications are often subjected to a high dose of radiation, and unlike traditional applications, it is not possible to frequently replace these power FETs (e.g., LDMOS). Therefore, it is essential to accurately predict the long-term integrated degradation of these power FETs in the presence of radiation. In this paper, we: (a) expose LDMOS transistors to various Total Ionizing Dose (TID) of gamma radiation and characterize the degradation in terms of threshold voltage shift (ΔV TH ), subthreshold slope (ΔSS); (b) quantify the dose- dependent generation of interface traps (ΔN IT ) and trapped charges (ΔN OT ) using a novel charge pumping technique; (c) introduce hot carrier degradation (HCD) models to explore the physical origin of the defects and their correlation with TID; and (d) establish the universality of the degradation kinetics and illustrate that the model and inferences drawn from the findings in this paper can be applied to other LDMOS devices as well. This analysis takes us a step closer towards a generalized TID-HCD model for power FETs that incorporates all sources of variation (electrical, thermal, and radiation) during device operations.

Junctionless FETs exhibit better high-temperature performance than their traditional inversion-mode (IM) counterparts due to reduced scattering in the substrate-oxide interfaces. In this work, a double-gate junctionless SiC FET with an embedded P+ pocket in the oxide layer (P+-SiCJLT) is studied for DC and AC performance for high-temperature and high-voltage applications using calibrated TCAD simulations. The advantages of P+-SiCJLT are manifold: (a) it offers efficient volume depletion and therefore can be scaled to lower channel lengths, (b) it improves the ON-state to OFF-state current ratio, (c) it improves the intrinsic gain, and (d) it promotes enhancement-mode operation in traditional depletion-mode FETs. These advantages become apparent when the P+-SiCJLT is compared with a device of similar dimensions without the P+ layer (SiCJLT). Moreover, P+-SiCJLT offers better electrostatics and $${{I}}_{{ON}}/{{I}}_{{OFF}}$$ ratio than a SiCJLT with P+ pockets near the source/drain regions (SDPocket-SiCJLT).

We have demonstrated modeling of phonon and defect-induced spin relaxation length (L-S) in Fe3O4 and organic semiconductor (OSC) Alq(3). L-S of Alq(3) decreases with enhanced disorder and film thickness at a low film width regime. Exponential change of L-S at low width regime is found for Alq(3) which is, however, absent for Fe3O4 indicating comparable spin-dependent scattering and L-S in Fe3O4. L-S also decreases with spin-flip probability both for Alq(3) and Fe3O4. Voltage-dependent tunnel magnetoresistance (TMR) response in Fe3O4/Alq(3)/Co and La0.7Sr0.3 MnO3 (LSMO)/Alq(3)/Co hybrid magnetic tunnel junction (MTJ) devices has been attributed to modified spin filter effect across magnetic/OSC junction at high bias regime. TMR reduction with Alq(3) thickness for Fe3O4 device has been attributed to spin relaxation at the organic spacer layer. A low bias peak from differential TMR indicates spin-polarized injection for both MTJ devices. Enhanced in-plane spin transfer torque for both MTJ is associated with modified spin filtering at magnetic/OSC junctions. Lower TMR signal for LSMO device indicates reduced tunneling and enhanced carrier injection across the OSC, which is also supported by the band structure profile. The TMR response observed from simulation results matches well with previously reported experimental results. Higher TMR response for Fe3O4 device indicates the possibility of device employment in room temperature magnetic recording applications.

Recently, back-end-of-line (BEOL) compatible indium oxide (In 2 O 3 ) thin-film transistors (TFTs), grown by atomic layer deposition (ALD) with channel thickness of ~1 nm and channel length down to 40 nm, have achieved a record high drain current of 2.2 A/mm at ${V}_{\textit {DS}}$ of 0.7 V. A systematic characterization of the reliability issues, such as positive bias temperature stress (PBTS) and hot carrier degradation (HCD), would allow its immediate integration into innovative ICs, such as 3D-stacked SRAM or on-chip bridge for mixed-voltage systems. Surprisingly, PBTS and HCD are both characterized by a universal two-stage threshold voltage shift ( $\Delta \!{V}_{\textit {th}}$ , a positive shift followed by a temperature-activated negative shift). This is attributed respectively to electron trapping/trap-generation and hydrogen-assisted formation of donor-traps. These competing mechanisms of $\Delta ~{V}_{\textit {th}}$ depend on the stress voltages and stress temperature. Unlike traditional logic transistors, HCD in BEOL-TFTs is strongly correlated to PBTS, caused by the much stronger vertical field in an ultra-thin device. Overall, this high-performance BEOL-transistor is remarkably reliable, with a relatively small $\Delta ~{V}_{\textit {th}}$ under PBTS/HCD stress conditions at room temperature (RT). However, self- and mutual heating of BEOL interconnect levels and the resultant threshold voltage variability must be mitigated/managed for its successful integration in various neuromorphic circuits.

LDMOS is one of the most widely used power transistors and has a variety of applications across multiple sectors (automobile, photovoltaics, communication, etc.). Unfortunately, the high applied bias makes Hot Carrier Degradation (HCD) a persistent reliability concern for LDMOS transistors. HCD occurs due to the generation of interface defects (NIT) by energetic electrons/holes, and the degradation rate depends sensitively on gate/drain voltages, doping, and transistor geometry. Several efforts have been made to model HCD in TCAD to predict the HCD susceptibility of next-generation LDMOS transistors. However, the lack of characterization techniques to extract NIT(x) in LDMOS makes it difficult to cross-check ΔNIT(x) obtained from the TCAD models, thereby making reliability aware predictive design difficult. In this paper, we: (a) determine the physical mechanism of HCD in a planar LDMOS using TCAD; (b) demonstrate the capability of the Super Single Pulse Charge Pumping (S2PCP) technique to extract NIT(x) at various points in the LDMOS, (c) quantify the spatial and temporal evolution of NIT(x,t), and compare the experimental results with TCAD predictions; (d) identify the key differences between the experimental and TCAD approach and suggest possible physical mechanisms responsible. This analysis establishes the robustness and identifies the limitations of TCAD modeling of HCD in LDMOS devices.

In2O3 vertical nanostructures (VNS) are fabricated using a glancing angle deposition (GLAD) technique upon an In2O3 thin film (TF) on a n-type silicon (n-Si) substrate. Analysis using high-resolution transmission electron microscopy (HRTEM) and high-resolution x-ray diffraction (HRXRD) revealed that the In2O3 VNS are amorphous in nature. An average ~4.5-fold enhancement in absorption was observed and a microscopic origin was proposed for observed bandgap changes for the n-Si/In2O3 TF/GLAD In2O3 VNS and bare n-Si/In2O3 TF samples in the visible region due to surface-related trap states or oxygen vacancies. The improvement in photodetection was attributed to the presence of a large number of surface-related trap states at the edge of metal contacts. The fabricated VNS detector possesses enhanced photosensitivity (~1.7-fold) due to an efficient photogating effect in the depletion region. A maximum detectivity of ~12.8 × 107 Jones was observed for the n-Si/In2O3 TF/GLAD In2O3 VNS device, which possesses ~15.6-fold enhanced detectivity as compared to the bare n-Si/In2O3 TF device.

Traditional charge pumping (CP) technique relies on trap-assisted recombination from the source/drain to the body contact to characterize interface trap density ( ${N}_{\text {it}}$ ) of classical bulk MOSFETs. A variant of the technique called single pulse CP (SPCP) allows interface trap characterization even if the bulk contact is absent, as in silicon-on-insulator (SOI) MOSFET. Unfortunately, neither technique is useful for devices with source-body-tied (SBT) and inhomogeneous channel doping profile, as in lateral diffused MOS (LDMOS) power transistors. Here, we propose a generalization of the CP/SPCP techniques, called Super SPCP ( $\text{S}^{{2}}$ PCP), to extract position-resolved localized degradations ( ${\Delta {N}}_{\text {it}}$ ) in an SBT LDMOS. Careful TCAD modeling and experimental characterizations demonstrate the effectiveness of the proposed approach. Our analysis provides deep insights into the physics of the SPCP technique, demonstrating that the approach can be used to characterize a variety of transistors with nontraditional doping profiles and contact configurations.

It is well-known that regardless of the voltage/temperature/device structure, the hot carrier degradation (HCD) of classical logic transistors scales onto a single universal curve, offering a theory-agnostic approach to predict long-term degradation based on short-term accelerated tests. Based on the experimental results, it has been suggested that the HCD in power transistors [e.g., laterally diffused MOS (LDMOS)] is structurally and functionally so fundamentally different that an analogous universal scaling cannot apply. This article uses a tandem FET (two MOS) model of an LDMOS to explore the physical origin of the anomalous HCD degradation in power transistors and establish the general principle needed to restore the universality of the degradation kinetics. Interestingly, the empirical models used to evaluate HCD degradation in power transistors emerge naturally as approximations of the generalized approach. This article establishes the fact that the physics of HCD is universal and provides an example of nonclassical but predictive degradation in power transistors. This takes us a step closer to a generalized HCD model encompassing all the devices, including logic, memory, and power transistors.

The impact of a high-performance nanostructured device using metal nanoparticle (NP) deposition is studied in this paper. Two devices, namely, a silver (Ag) NP coated indium oxide (In2O3) nanostructured device and a bare In2O3 nanostructured device, were fabricated by glancing angle deposition aided electron beam vacuum coating system to study the impact of Ag NPs over In2O3 nanostructures. The morphology of Ag NPs, as-fabricated nanostructures, and growth regions was analyzed using field emission scanning electron microscopy. The formation of Ag3O4 monoclinic crystal structures was confirmed by high-resolution x-ray diffraction profiles. The current density (J)-voltage (V) plot shows the modulating performances of an Ag NP coated In2O3 nanostructured device due to the occurrence of trap states originated from the incorporation of Ag NPs. For in-depth analyses of the impact of Ag NPs, frequency-dependent capacitance (C)-V, conductance (G)-V, and impedance (Z)-V characteristics were analyzed. A free charge carrier concentration (Nd) of ∼8.23 × 1016/cm3, a trap concentration (NT) of ∼1.48 × 1017/cm3, and a significant increment in conductance were observed for an Ag NP coated In2O3 nanostructured device (∼23.36 μS) than the bare In2O3 nanostructured device (∼13.05 μS) at a high frequency of 2 MHz. The delta-depletion model was implemented to obtain the C-V plots to match the experimental data adequately. The Ag NP coated In2O3 nanostructured device was further investigated by an analytical series circuit model, which manifests that the device can be used as catalysts, medical devices, etc.

In this paper, we focus on the implications of self-heating effect (SHE) on hot carrier degradation of CMOS and more-than-Moore devices. We explain how hot carrier degradation, while having the same basic underlying physics, affects an LDMOS or an NCFET in very different ways compared to a planar or a FinFET transistor, suggesting a need and opportunity for developing a theory of hot carrier degra...

Since the 1970s, LDMOS transistors have been used in a variety of applications because of their versatility and monolithic integration with CMOS logic. Despite the advantages, interface defects (N IT ) generation due to Hot Carrier Degradation (HCD) has been a persistent reliability challenge for LDMOS transistors. Unfortunately, neither classical charge pumping nor single-pulse charge pumping techniques can be used to locate/quantify N IT in a source-body-tied LDMOS configuration. Here we: i) identify the multiple hotspots of HCD in an LDMOS using experimentally validated TCAD simulations; ii) introduce and implement a TCAD-enabled novel charge pumping technique to probe region-specific interface states in a source-body-tied (SBT) LDMOS; and iii) develop a unified multi-hotspot HCD model to interpret the degradation kinetics in power transistors. The analysis provides deep insights into the HCD in an LDMOS and the generalized charge pumping technique can be used to map interface states in a variety of transistors with non-traditional doping and contact configurations.

The emergence of several technology options and the ever-broadening range of applications (e.g., automotive, smart grids, solar/wind farms) for power electronic devices suggest both a need and an opportunity to develop unifying principles to guide the development of wide bandgap (WBG) semiconductors. Unfortunately, power electronic devices are typically evaluated with a variety of elementary figure of merits (FOMs), which offer inconsistent/contradictory projections regarding the relative merits of emerging technologies. Indeed, one relies on the empirical (extrinsic) safe-operating area (SOA) of a packaged device to ultimately assess the performance potential of a technology option. Unfortunately, extrinsic SOA can only be calculated a posteriori, i.e., after precise measurement of the fabricated device parameters, making it suitable only for relatively mature technologies. Based on the insights of material-device-circuit-system performance analysis of a variety of idealized WBG power electronic devices (e.g., GaN HEMT, ${\beta }$ -Ga 2 O 3 MOSFET), in this paper, we analytically derive a comprehensive, substrate-, self-heating-, and reliability-aware “intrinsic/limiting” safe operating area (SOA) that establishes a priori , i.e., before device fabrication, the optimum and self-consistent trade-off among breakdown voltage, power consumption, operating frequency, heat dissipation, and reliability. We establish the relevance of the intrinsic-SOA by comparing its prediction with a broad range of experimental data available in the literature. In between the traditional FOMs and extrinsic SOA, the intrinsic SOA allows fundamental/intuitive re-evaluation of intrinsic technology potential for power electronic devices and identifies specific performance bottlenecks and suggests strategies to circumvent them.

In this report, Ag nanoparticles were fabricated using the single-step glancing angle deposition (SS-GLAD) technique upon In2O3/TiO2 thin film. Afterward, a detailed analysis was done for the two samples such as In2O3/TiO2 thin film and In2O3/TiO2 thin film/Ag nanoparticles, to inspect the field emission scanning electron microscopy (FESEM), energy-dispersive X-ray analysis (EDAX), X-ray diffraction (XRD), ultraviolet (UV) spectroscopy, and electrical properties. The reduction in bandgap energy for the samples of In2O3/TiO2 thin film/Ag nanoparticles (~4.16 eV) in comparison with the In2O3/TiO2 thin film (~4.28 eV) was due to trapped e–h recombination at the oxygen vacancies and electron transmission of Ag to the conduction band of the In2O3/TiO2 thin films. Moreover, under irradiation of photons Ag nanoparticles generated inorganic Ag–O compound attributable to the localized surface plasmon resonance (LSPR). Also, a ~90% high transmittance, ~60% and ~25% low reflectance in UV and visible region, fill factor (FF) of 53%, as well as power conversion efficiency (PCE) of 15.12% was observed for In2O3/TiO2 thin film/Ag nanoparticles than the In2O3/TiO2 thin film. Therefore, the use of Ag nanoparticles textured In2O3/TiO2 thin film–based device is a promising approach for the forthcoming photovoltaic applications.

Silicon carbide (SiC) is the material of choice for high-temperature, high-voltage, and other harsh environment applications in high-energy physics, outer space, etc., because of its high critical electric field and radiation tolerance. In this work, single- and double-gate junctionless transistors (SGJLT, DGJLT) are studied extensively using TCAD device simulations, taking SiC as a substrate material. Junctionless transistors (JLTs) offer better high-temperature performances compared to a conventional metal-oxide-semiconductor field-effect transistor (MOSFET). To investigate the temperature dependence of the drain current (ID), the intrinsic gain is studied for the devices under high-temperature conditions. Unlike a conventional MOSFET, at the zero temperature coefficient (ZTC) point, output current slightly increases with temperature for a JLT, which is beneficial in electronics applications at high temperatures. After the ZTC point, the output current decreases with an increase in temperature, similar to a conventional MOSFET. Taking the advantages of high-performance JLT, SiC device's compatibility with high temperatures and high voltages, a boost converter has been designed. It was shown that efficiencies as high as 80% can be achieved even at temperatures of 380K.

Unlike traditional logic transistors, hot carrier degradation (HCD) in power transistors involves simultaneous and potentially correlated degradation in multiple regions. One must deconvolve and characterize the voltage- and temperature-dependence of these region-specific degradations to develop a predictive HCD model of power transistors. Unfortunately, power transistors' doping and geometrical complexities make it challenging to use traditional defect-profiling techniques, such as charge-pumping or gated-diode methods. This Letter uses a physics-based tandem-FET model of an Laterally Diffused MOS (LDMOS) transistor to develop a “three-point I–V spectroscopy” technique that uses the time-evolution of three critical points of the measured I–V characteristics to extract mobility and threshold voltage degradations in the channel and drift regions. This innovative approach should generalize to other configurations of the LDMOS transistor as well.

Although the CMOS-compatible Laterally Diffused MOSFET (LDMOS) is widely used in various applications as a versatile and efficient power electronic device, its hot carrier degradation (HCD) remains a persistent and important design challenge. None of the classical HCD models apply, because the geometric and doping complexities of the channel and drift regions create multiple hotspots with bias-dependent hot carrier injection into the oxide. To address these challenges, here we: 1) propose a novel geometrical partition of the LDMOS and represent each part by a TCAD-calibrated and experimentally validated tandem-FET compact model; 2) use the new compact model to propose an ` I - V spectroscopy' methodology to deconvolve mobility and threshold degradation in the channel and the drift regions; 3) separate the degradation in the two regions by postprocessing measured I-V curves; 4) demonstrate that ΔV th determined by classical techniques, e.g., constant current (CC) or maximum transconductance (Gmmax), are contaminated by mobility degradation and must be corrected by the proposed technique for accurate lifetime projection.

A capacitive memory effect has been reported for Ag nanoparticles (NPs) sheltered In 2 O 3 nanowires (NWs) devices. To compare the performance with that of bare In 2 O 3 NWs, two devices (viz. In 2 O 3 NW/Ag NPs and In 2 O 3 NW) were fabricated on n-Si substrate inside the electron beam (e-beam) evaporator using the double-step glancing angle deposition (GLAD) technique. The field emission scanning electron microscopy (FESEM) shows the formation of In 2 O 3 NWs and Ag NPs. The high-resolution transmission electron microscopy (HRTEM) shows the formation of uneven NWs and selected area electron diffraction (SAED) analysis confirmed the amorphous nature of the NWs. An averagely ~7.5 and ~9.3 fold enhanced absorption was observed in the UV region and visible region for In 2 O 3 NW/Ag NPs. The modulation in current density of ~4.5 fold at +10 V and ~5.7 fold at -10 V were observed for the fabricated In 2 O 3 NW/Ag NPs MOS device. At 2 MHz frequency response, the In 2 O 3 NW/Ag NPs device depicted a low interface trap density (Dit) of ~0.2 × 10 10 cm -2 eV -1 . The maximum memory window of 5.61 V at ±8 V was extracted for the In 2 O 3 NW/Ag NPs device from the large C-V hysteresis curve, thus establishing a strong presence of memory window in the device.

SiOx nanodots were fabricated on a TiO₂ thin film using glancing angle deposition technique. The fabricated samples were annealed at 950 °C in open air configuration to obtain Si nanoclusters resulting from phase separation of SiOx nanodots. Field Emission Gun Scanning electron microscopy and atomic force microscopy were used to examine the topography of the samples. The elemental composition of the samples was analyzed using energy dispersive X-ray mapping and their crystallinity was confirmed by analyzing the bandgap determined from the Tauc plots. The annealed samples show a broadband absorption which is about two folds in magnitude as compared to the as deposited (unannealed) samples. The photoluminescence spectra confirms the quantum confinement effect in the annealed samples. A photodetector was fabricated from an annealed sample by depositing gold contacts on top of it. This photodetector showed a two-fold increase in dark current and a 1.5-fold increase in light current compared to a photodetector made from the as-deposited SiOx samples-which is due to the increased crystallinity in Si nanoclusters. Finally, the rise and fall times of the device were measured through a switching experiment.