Recently, major semiconductor manufacturers have developed spin-transfer torque magnetic random-access memory (STT-MRAM) embedded in logic node due to its superior properties. In order to leverage high performance in advanced logic node, it continues to scale down logic node from 28nm to 14nm and 8nm. As device dimensions shrink, variability in magnetic and electrical properties increases, impacting data retention, endurance, and read/write performance. In this paper, we review the overall reliability trends, highlighting specific reliability factors that demonstrate significant scaling dependence.
Gate dielectric time-dependent dielectric breakdown (TDDB) is a critical reliability concern in FinFET devices. However, the microscopic failure mechanism of on-state TDDB (|V-gs|>0, |V-ds|>0) is different from V-gs-only TDDB (|V-gs|>0, |V-ds|=0) due to the impact of channel current. In this study, aberration-corrected scanning transmission electron microscopy (STEM) and advanced strain analysis are employed to observe the physical evolution during the breakdown process of FinFETs from an atomic perspective. It is discovered that breakdowninduced silicon epitaxial defects are generated at the corners of the fin for Vgs-only TDDB, while shifted to the middle of the fin for on-state TDDB. The formation of these defects on the Si <110> orientation is accompanied by tensile strain. This work provides new insights into different types of TDDB phenomena in FinFETs at the atomic scale.
Electrostatic discharge (ESD) protection design for radio-frequency integrated circuits (RFICs) and high-speed I/O circuits is a challenge due to the parasitic capacitance generated from ESD devices, which significantly degrades circuit performance under high-frequency/high-speed operation. Striking a balance between effective ESD protection and maintaining high-frequency/high-speed circuit performance is strongly requested by IC industry. In this work, an improved layout is proposed to significantly reduce the parasitic capacitance of the diode-trigger silicon-controlled rectifier (DTSCR) device while maintaining high ESD robustness. The DTSCR with improved layout has been verified in a 28-nm fully-silicide CMOS process with the experimental result of high ESD robustness per unit capacitance, which is suitable for on-chip ESD protection design with low-C requirement.
AC TDDB (Time-Dependent-Dielectric-Breakdown) lifetime exhibits inconsistency at low frequencies (<10kHz), while it is reported to be longer at higher frequencies. In this study, AC TDDB mechanism is systematically investigated over a frequency range of 2Hz to 500kHz. Notably, n-type transistors with bi-layer gate stack demonstrate degradation of AC TDDB lifetime below that of DC TDDB in both FinFET and Planar devices. This degradation worsens as the gate oxide thickness decreases, a phenomenon explained by Maxwell-Wagner instability. To mitigate this degradation at low frequencies (LF), applying a small positive voltage during the off-state of the AC pulse (Vr) can improve reliability, particularly in circuits operating at low frequencies.
Reliability investigations of La-doped and Al-doped ZrO2 are performed. Higher doping concentrations are found to decrease the leakage current and increase the breakdown voltage. Time dependent dielectric breakdown characterizations were performed at various temperatures. The role of energetic carriers in the wear-out and breakdown process is demonstrated, supporting the use of power law lifetime models. The breakdown defect density is shown to decrease at higher temperature. Finally, an Arrhenius temperature dependence of the hard breakdown failure times is observed. A resulting apparent zero field activation energy of around 1.9 +/- 0.1 eV is found on the three doped dielectrics.
Investigating oxide defect-induced random telegraph noise signals within stress-induced leakage current is a key approach for understanding the degradation of thin oxides in deeply-scaled devices. However, experimentally measured time-resolved gate leakage current at a constant stress voltage often includes non-constant baseline profiles due to various drift-contributing components. We introduce an algorithm that isolates pure stress-induced leakage current information from gate leakage current data by extracting the underlying baseline profile without prior assumptions. Using a Monte Carlo-generated representative dataset, we demonstrate statistically robust extraction of an arbitrary baseline profile. Subsequently, the algorithm's performance on various baseline profiles is validated, and the significance of baseline correction is highlighted by analyzing random telegraph noise signals in an experimental dataset before and after correction.
In this paper, Hot Carrier Degradation (HCD/HCI) characterization results measured on Low VT N-channel Metal Oxide Semiconductor Field Effect Transistors (NMOSFETs) used in Dynamic Random Access Memory (DRAM) for mobile and automotive applications are presented. Dependence of HCD on Gate Voltage Stress (VGSTR), Drain Voltage Stress (VDSTR), and Stress Temperature (T) are investigated and analyzed. Degradation mechanisms at various conditions are proposed based on the experimental signature of the measured data. Parametric degradation at end-of-life (EOL) is predicted with conventional exponential VDSTR model and benchmarked against an augmented VDSTR dependence model that is calibrated across wide range of data.
This study reports on the thermomechanical fatigue behavior of two-level Cu interconnects under surge current conditions. Standard two-level Cu interconnects of varying dimensions were subjected to high-density, shortduration current pulses, with resistance evolution monitored as a failure indicator. Experimental and computational analyses reveal that interconnect width and thickness significantly influence failure susceptibility, highlighting the roles of localized Joule heating, thermal expansion mismatch, and plastic deformation in damage progression. Additionally, the results indicate the existence of a critical current density (or power density) below which fatigue failure does not develop, suggesting an endurancelike behavior in Cu interconnects. The study also emphasizes the importance of considering temperature effects, as recovery and recrystallization may counteract the accumulation of plastic energy, thereby suppressing fatigue failure. These findings provide critical insights into the fundamental fatigue mechanisms of Cu interconnects and inform design strategies for improving their resistance to transient high-current events in semiconductor applications.
Developments in backside power delivery (BPD) technology will become increasingly important for advanced semiconductors, but will present new challenges for failure analysis (FA) labs. Electro-Optical TeraHertz Pulsed Reflectometry (EOTPR) is a well-established electrical FA technique for package level open and leakage faults, but has comparatively little use for detecting die-level faults. Here, two case studies are presented that demonstrate how EOTPR can be used to localize faults within a die, highlighting how EOTPR could be utilized for BPD devices. Recent and future key developments in EOTPR are also presented.
Magnetic random-access memory (MRAM) shows great promise as an embedded working memory solution for data-intensive high-performance computing (HPC) and artificial intelligence (AI) applications. It requires not only high speed but also exceptional endurance performance. In this study, we discovered that current impact plays a critical role in bipolar stress (relative high voltage) and decreased while operating (relative low voltage). By integrating existing breakdown physics, a new model incorporating self-heating to estimate endurance is developed. The endurance model is used to identify the optimal operation window for maximal endurance in 1T1R MRAM cell.
This study investigates the reliability of enhancement-mode GaN-HEMTs with ferroelectric gate dielectric stack under High Temperature Gate Bias (HTGB) and Dynamic Gate Stress (DGS) conditions. The gate Time To Failure (TTF) is analyzed across varying gate voltages (VG), temperatures (T), switching frequencies (fS) and duty cycles (D). Under static HTGB stress, wear-out mechanisms leading to gate breakdown show no dependence on the gate's perimeter or area, suggesting that failure is localized to specific high-stress regions, such as gate corners. Lifetime projections under HTGB at 150 degrees C estimate a maximum VG of similar to 9.6 V for a 10-year lifetime. In contrast, under pulsed DGS conditions, a higher VG is achievable, possibly due to charge recovery during OFF-states. Finally, the DGS analysis further reveal that D plays a fundamental role in mitigating damage, while fS has negligible impact.
Magnetic Random Access Memory (MRAM) is one of the most promising candidates to replace eFlash as the embedded non-volatile memory in microcontroller units at advanced CMOS nodes for automotive application. In addition to serving as random-access memory for code and data storage, it can be adapted to function as one-time programmable memory (OTP), irreversible and resistant to magnetic interference, making it ideal for storing critical data such as encryption keys or security codes. Integrating OTP into an MRAM main array demands rigorous consideration to ensure macro reliability. This paper provides a model to assess design-technology-reliability co-optimization margin at early development stage. The model includes factors of OTP array size, magnetic tunnel junction (MTJ) film property and dimension, operation temperature, as well as process variation.
The Microsanj Thermal Reflectance (TR) Imaging method [3] for locating open circuits enables new Failure Analysis (FA) paths for direct examination of defects. This method increases the probability of finding the root cause for open lines in flexible package traces. The method uses X-ray, C-SAM (Scanning Acoustic Microscopy) and Thermal imaging as non-destructive methods to locate open faults. This process was used to conduct electrical tests and destructive analysis to examine a failing flexible ribbon cable. The result thermal imaging data showed the location of an open fault in the cable signal trace without causing any disruptive damage to the sample under evaluation. Later laser exposure was used to remove the insulation material to confirm the location of the open fault in the sample under evaluation by optical imaging and electrical check. This paper demonstrates that Microsanj TR Imaging can provide clear visual results of open faults in metal traces found in flexible ribbon cables and flex circuits down to a resolution of several microns for failure analysis.
This study investigates the impact of short-term high-temperature operating life (HTOL) reliability testing on the trapping behavior and power performance of carbon-doped AlN/GaN/AlGaN High Electron Mobility Transistors (HEMTs). HTOL stress can lead to significant degradation in key performance metrics, including output power (Pout) and power-added efficiency (PAE), primarily due to increased current collapse and knee walkout. Transmission Electron Microscopy (TEM) analysis revealed the formation of voids at the gate foot on the drain side, indicating physical damage. Drain current transient spectroscopy (DCT) revealed post-stress changes in trap dynamics, including the emergence of a secondary emission process (E2). Further analysis attributed E2 to the overlap of enhanced emission from a field-dependent deep-level trap (E1, activation energy similar to 0.7 eV) and a stress-induced increased density of traps with distributed energy level.
In this paper, we report on the charging damage observed in capacitors situated within a single Deep N-Well (DNW) during integrated circuit processing. These capacitors, connected between VDD and VSS within a single power domain, accumulate charge from backend metal/via antennas during plasma etching. Our study delves into the behavior and mechanisms underlying this charging damage, utilizing extensive test-patterns. Based on the results and the identified mechanisms, we propose the layout and design guidelines to mitigate such damage.
Stress migration (SM) in back-end-of-line (BEOL) copper interconnections is a key factor in evaluating the reliability of semiconductor processes. Copper voids tend to aggregate in areas with higher stress gradients, leading to interconnections with high resistance or open circuits, which can ultimately cause device failure in the copper interconnect process. In traditional SM failure analysis, the primary method to depict stress gradients is by examining abnormal profiles where stress-induced voids have aggregated. However, this approach cannot directly capture material change. In this study, we have successfully introduced the Kernel Average Misorientation (KAM) map of Electron Back Scatter Diffraction (EBSD) to analyze stress gradients distribution indirectly in metal's intrinsic quality changes.
This work presents the results of monitoring aging behavior at cryogenic temperature using a synthesizable, calibration-free on-chip reliability sensor. The odometer is based on the beat frequency technique, and it measures aging degradation at cryogenic temperature within microseconds, effectively mitigating inaccuracies caused by aging recovery. By detecting frequency shifts as small as 0.01%, the sensor demonstrates exceptional sensitivity, making it particularly wellsuited for analyzing cryogenic test results. Experiments on 28nm planar and 12nm bulk FinFET technologies show very low degradation at cryogenic temperature after only two days of stress testing. These findings emphasize the efficiency of on-chip sensors in facilitating precise reliability analysis under extreme environmental conditions, underscoring their potential for future applications in high-performance and space-grade systems.
Silicon carbide MOSFETs have been tested under gate switching stress conditions with an operation frequency of 1.0 MHz until 1012 cycles. The resulting threshold voltage drift was described by a power law and saturation effects have been observed for two out of three manufacturers. Further, the impact of the threshold voltage drift on switching transients was examined in double pulse tests and the resulting switching losses have been calculated. For one manufacturer the threshold voltage increased by almost 120 %, elevating the total switching losses by approximately 8 %. Due to the higher threshold voltage, resulting from gate switching stress, turn-on events were decelerated, whereas turn-off evens accelerated for all observed manufacturers.
This study comprehensively investigates the impact of gamma radiation on the DC, pulse, and RF performance of GaN-on-Si MIS-HEMTs exposed to a total dose of 100 kGy. The DC performance reveals an enhancement in drain current and transconductance along with reduced contact and sheet resistance, as confirmed through input, output and TLM measurements. Breakdown analysis further supports these improvements, revealing decreased leakage currents across the gate, drain, and buffer, which lead to reduced leakage paths and higher breakdown voltages. Furthermore, the pulse I-V measurements show minimal threshold voltage shift and reduced current collapse, providing evidence of diminished trapping sites in the gate-drain access region post-gamma radiation. The study also explores improvements in small-signal (f(T) and f(MAX)) and large-signal (eta) RF figures of merit, as evidenced by S-parameter and load-pull measurements. These experimental findings highlight the exceptional robustness of GaN-on-Si MIS-HEMTs under gamma radiation, enhancing their suitability for harsh and space applications.
