TNODE: A Low Power Sensor Node Processor for Secure Wireless Networks.

Goran Panic,Oliver Schrape,Thomas Basmer,Frank Vater,Klaus Tittelbach-Helmrich

International Symposium on System-on-Chip (SoC)（2013）

IHP

被引用6|浏览35

摘要

In this paper we describe a sensor node crypto processor designed for use in wireless sensor networks with strong security demands. The presented system-on-chip is a mixed-signal processor-based design containing the hardware crypto accelerators (AES, ECC, SHA-1) that provide the means for secure communication in the network. The unique system architecture combines an asynchronous processor core with synchronous peripherals resulting in a low-power system operation. The designed chip integrates an embedded Flash memory and a 12-bit ADC making it a suitable solution for small-size sensor node devices. The paper describes the chip architecture and discusses the most important implementation and verification issues. Finally, the results of the chip measurement have been presented.

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关键词

analogue-digital conversion,asynchronous circuits,cryptography,embedded systems,flash memories,integrated circuit design,low-power electronics,mixed analogue-digital integrated circuits,system-on-chip,telecommunication security,wireless sensor networks,ADC,AES,ECC,SHA-1,TNODE,asynchronous processor core,chip architecture,chip design,embedded Flash memory,hardware crypto accelerators,low power sensor node processor,low-power system operation,mixed-signal processor-based design,secure communication,secure wireless networks,security demands,sensor node crypto processor,small-size sensor node devices,synchronous peripherals,system architecture,system-on-chip,wireless sensor networks,word length 12 bit