This paper presents the activities of IHP within the Green ICT project, which aims to provide measurement centers and testbeds to collect data relevant for the life cycle assessment of millimeter-wave and sub-THz communication devices. These include the setup of an anechoic chamber and a near-field scanner for the characterization of radios and antennas, as well as the construction of a standalone 5 G testbed for real-time outdoor experiments on fronthaul and backhaul data links. The installed measurement infrastructure was validated by measurements on reference designs.

This paper presents two wideband power amplifiers (PA) for future 6G wireless communications. One-way and two-way stagger-tuned PAs are designed and fabricated in 130-nm SiGe BiCMOS technology with heterojunction bipolar transistors (HBT) with ft/fmax of 300 GHz and 450 GHz, respectively. Large-signal wideband operation of the one-way PA is achieved by a transformer-based output power matching. A high magnetic coupling power combining transformer and balun is utilized for the output power matching of the two-way PA leading to wideband yet low-loss matching. The one-way PA covers the entire D-band in terms of 3-dB bandwidth. It achieves an output P1dB of 11 dBm and a maximum PAE of 5%. The two-way PA has a 3-dB bandwidth of 48 GHz centered around 140 GHz. It delivers linear power up to 13 dBm. The one- and two-way PAs show a gain of 30 dB and 22 dB, and their cores occupy a silicon area of 0.145 mm2 and 0.2 mm2, respectively.

The ever-growing complexity of modern systems as well as the shrinking time to market enforces the use of already designed hardware components i.e. hard and soft IP cores. The fact that also requirements with respect to security significantly increased and that side-channel analysis (SCA) attacks are meanwhile a well-known threat it is paramount to ensure SCA resistance of ASICs and FPGA implementations derived from cryptographic IP cores. This requires to evaluate this feature for each IP core and target technology even down to the level of the cell library. The experiments reported here clearly show that the three available cell libraries even though developed for the same 130nm technology of IHP exhibit different sensitivity to SCA attacks ranging from quite resistant to very vulnerable.

The project “Hardening the value chain through open-source, trustworthy EDA tools and processors (HEP)” uses open-source, free components and tools for the production of a prototypical security chip. A design flow using only free and open tools from the abstract description in SpinalHDL via OpenROAD down to the GDS-file for tape-out has been established, and first ASICs produced at IHP. The prototypical hardware security module (HSM) produced in this way provides, among other things, a processor based on VexRiscv, a cryptographic accelerator and masking of cryptographic keys. The open development tools used in the process were integrated into a common environment and expanded to include missing functionality. Subsequently, the whole tool chain and its peripherals are wrapped into a new Nyx container. The easy accessibility of the used process significantly reduces the learning curve for chip design. Additionally, we provide tools for formal verification and masking against side-channel attacks in our design flow. Interest in the results of project HEP has been shown in publications in which industrial partners participated, such as Elektrobit, Hensoldt Cyber, IAV, Secure-IC and Swissbit Germany.

In this paper, we present a fully integrated four-channel receiver (Rx) designed to operate over a wide frequency range in D-Band. The chip has been implemented in a 130 nm SiGe BiCMOS technology process and validated by measurements. The paper also presents the concept of the Rx-chip integration into an Antenna-in-Package (AiP) module, which is currently being implemented.

We present the fabrication and testing of a prototype high-speed, quad-channel mid-board optics transceiver chipset and module applicable to VCSEL-based intra-satellite optical interconnects. The optical transceiver (OTRx) chipset comprises a VCSEL driver and a TIA integrated circuit (IC) both manufactured in IHP 130 nm SiGe BiCMOS process. The 4-channel OTRx module operates at 850 nm wavelength. It features low power consumption, a small form factor and it is pluggable on the host board through a micro edge card (MEC) connector. We present first functional test results in loop-back configuration at data rates up to 15 Gb/s per channel. The work is performed within the framework of H2020-SPACE-SIPHODIAS project. Additional presentation content can be accessed on the supplemental content page.

This paper proposes an optimized pipelined decoding architecture with seven processing stages for unrolled LDPC decoders. Pipelined design with seven register layers significantly increases the resulting clock frequency. Moreover, we investigate the optimal layout shape for unrolled decoders. This paper's fastest decoder is based on the IEEE 802.11n LDPC(1944,1620) parity-check matrix and achieves 2937 Gb/s of coded throughput after physical design. By optimizing the pipeline, floorplan, and employing a codeword length of 1944 bits, we increased the throughput by 241% compared to the previous fastest LDPC decoder presented in the literature. To the best of our knowledge, it is the fastest soft-decision decoder published so far. The standard min-sum approach is employed for decoding, and the proposed improvements consider changes only on the hardware level.

In past years, Parallel Sequence Spread Spectrum (PSSS) has attracted significant attention as a modulation technique for wireless communication systems targeting data rates of 100 Gb/s and beyond. PSSS allows designing high-speed baseband processors, which can be partially implemented in the analog domain. It uses multiple analog-to-digital converters (ADCs) to sample the received baseband signal in parallel, significantly relaxing the sampling rate and ADC complexity. However, due to the sidelobe effects of bipolar $m$ -sequences, PSSS shows lower performance than standard digital modulation schemes. This paper proposes real-valued PSSS spreading sequences with attenuated autocorrelation sidelobes. Such sequences show excellent bit error rate (BER) performance. Moreover, our sequences do not have length restrictions of 2m – 1, like in the case of $m$ -sequences, and reduce the chip area required to implement PSSS transceiver. The proposed sequences also reduce the peak-to-average power ratio (PAPR) of PSSS.

This paper reports our latest implementation results of a fully unrolled LDPC decoder prototyped in 28 nm CMOS technology. The decoder achieves 1218 Gbps coded throughput and consumes a 5.49 mm 2 chip area. The standard min-sum decoding algorithm with four-bit quantization, five unrolled iterations, (648,540) parity matrix, and a seven-stage pipeline is employed. Such implementation achieves a higher data rate than adaptive degeneration and finite-alphabet decoding algorithms, requires less silicon than the solutions mentioned above, and is fully compliant with the IEEE 802.11n WLAN standard.

The key computation in the min-sum decoding algorithm of a Low-Density Parity-Check (LDPC) is finding the first two minima and also the location of the first minimum among a set of messages passed from Variable Nodes (VNs) to Check Nodes (CNs) in a Tanner graph. In this paper, we propose a modified rejection-based scheme for this task which is able to find the one-hot sequence of the minimum location instead of its index. We show that this modification effectively reduces the complexity of min-sum decoding algorithm. Additionally, we reveal a pipelining potential in such a rejection-based architecture which facilitates the multi-frame decoding of Low-Density Parity-Check (LDPC) codes and therefore results in an improvement in decoding throughput with bearable hardware overhead. Synthesis and floorplanning in an industrial 28 nm CMOS technology show improved results in terms of throughput, power, and chip area.

With the growth of system complexity, the use of previously designed components, IP cores, has become a usual practice in hardware design. Nowadays, many companies offer a broad range of IP solutions available for use in ASICs as well as FPGA designs. In this paper we concentrate on the use of soft crypto IP cores, i.e. the cores designed to address security issues. The intention is to raise the awareness of the designers about the possible vulnerabilities that may be acquired with such pre-designed IP blocks if no additional security evaluation was performed. We show on the example of an internally-developed cryptographic core, how the security strength of the design depends on the applied semiconductor manufacturing process and the logic gate libraries.

This paper presents a broadband high-gain and high-linearity four stages cascode Low-Noise Amplifier (LNA) implemented in 0.13 ${\mu} \mathbf{m}$ SiGe BiCMOS technology. Gain, Noise Figure (NF) and stability have been improved by employing two techniques; shunt-peaking at the intermediate node of the cascode devices, and negative capacitor feedback of the common base device. Wideband flat gain has been achieved by using staggered-tuning technique. The designed LNA has gain and NF of 30 dB and 7.5 dB, respectively. It covers the entire D-Band with a DC power consumption of 100 mW and the total chip area is 0.44 mm2 including PADs.

This paper compares three hardware variants of successive cancelation (SC) decoders for polar codes. The fastest implementation, based on the basic SC, provides decoding throughput up to 1700 Gb/s, when implemented in a 28 nm CMOS technology at the worst-case timing corner. This is the fastest polar decoder published so far, to the best of our knowledge. We also discuss the difficulties of implementing single-parity-check nodes and repetition nodes in fast simplified SC (Fast-SSC) decoding algorithm. These two node types are the primary sources of clock frequency reduction, and special care needs to be taken when these elements are implemented. The Fast-SSC decoder requires ~3 times fewer hardware resources than the base version of SC, but achieves ~10% lower decoding throughput.

The magnitude of soft error rate (SER) of integrated circuits (ICs) utilized in space missions is jeopardized due to the inconsistent intensity of radiation exposure. To protect critical electronic elements and ensure desired system performance, it is necessary to establish the real-time detection of space particle events (SPE). This research study assesses eight supervised machine learning algorithms by varying history data length (3 to 24 hours) to predict the occurrence of SPE one hour ahead. Customized SPE hourly predictor based on logistic regression is chosen for hardware implementation owing to high prediction accuracy (96.35%) as well as simplicity. After that, the optimal prototype design of the logistic regression algorithm is implemented on Field Programmable Gate Array (FPGA) with affordable hardware footprint. Finally, the digital design tested on FPGA is simulated to generate an application-specific integrated circuit (ASIC) chip layout (industrial 130 nm) integrated with SPE hourly predictor.

The energy efficiency of wireless sensor nodes is determined by the power efficiency of underlying hardware, network topology and the profile of target application. In this paper, we present the methodology aimed to select optimal power saving strategy when designing an embedded sensor node microcontroller for specific application. The goal of presented methodology is to select the best-suited power saving techniques to be implemented in sensor node hardware based on the activity profile of the target application. The paper describes applied approach and shows the results of the microcontroller implementation targeting security demanding sensor network applications.

In this paper, we propose pipelining and unrolling schemes for ultra-high speed belief propagation polar decoders. The proof of concept implementation in 28 nm CMOS technology achieves 1380 Gbps of coded throughput with a short polar codeword length of 512 bits, placing it as one of the fastest soft-decision FEC implementations published so far. With a codeword of length 1024 bits, the decoding throughput can be even higher. Moreover, the decoder shows better error correction performance than other ultra-high speed polar decoders published recently. The consumed chip area is 5.98 mm 2 , and the chip uses five unrolled iterations with constant quantization of four bits at every processing stage.

This paper presents a differential frequency quadrupler (FQ) for future 6G wireless communications based on two cascaded bootstrapped Gilbert cells (GC) with a high broadband in-band harmonic rejection. This rejection is achieved through careful adjustment of the transmission line electrical length at the bootstrapped GC. The FQ is fabricated in a 130-nm SiGe BiCMOS technology with heterojunction bipolar transistors (HBT) with an ft / fmax of 300 GHz and 450 GHz, respectively. The FQ covers the entire D-band from 110 to 170 GHz and delivers a maximum output power of +2.5 dBm with a peak gain of 11 dB and a high power-added efficiency (PAE) of up to 2.2%. Within the entire D-band, the FQ achieves a minimum harmonic rejection of 29 dBc, which - to the best of the author's knowledge - is the highest among any reported work at a comparable operational bandwidth without filters. The presented chip occupies an area of 0.7mm2 including pads and draws a DC current of 33 mA from a 3.3 V power supply.

A fully unrolled fully parallel decoding architecture for Low-Density Parity-Check (LDPC) codes is proposed in this paper. Specifically, the iterations of a min-sum decoding scheme are also unrolled and each is implemented with a separate dedicated hardware. The proposed architecture implemented in a 28 nm CMOS technology is able to achieve the throughput of 550 Gbps, occupying an area of 4.98mm 2 . These results are accomplished with 4-bit quantization of the min-sum decoding messages and six iterations in the case of a (648,540)-LDPC code from IEEE 802.11n. The results show improvements compared with the adaptive degeneration [1] and finite-alphabet [2] decoding algorithms, in terms of both throughput and chip area.

Solar Particle Events (SPEs) generate cosmic radiation of different magnitude in a time span of several hours or even days. This contributes to an increased probability of higher magnitude Single-Event Upsets (SEUs) occurrence in space applications. It is critical to establish early detection of SEU rate or Soft Error Rate (SRE) changes to enable timely radiation hardening measures. This research paper focuses on the high-accuracy detection of SPEs using the manually collected space data. Additionally, the prediction of SRE increase or decrease was established with the seven widely used supervised machine learning algorithms. Excellent performance of 97.82%, including a high F1-score, was achieved during the presence of SPE using $k$ -Nearest Neighbor algorithms.

We report the design of a 112 Gb/s radiation-hardened (RH) optical transceiver applicable to intra-satellite optical interconnects. The transceiver chipset comprises a vertical-cavity surface-emitting laser (VCSEL) driver and transimpedance amplifier (TIA) integrated circuits (ICs) with four channels per die, which are adapted for a flip-chip assembly into a mid-board optics (MBO) optical transceiver module. The ICs are designed in the IHP 130 nm SiGe BiCMOS process (SG13RH) leveraging proven robustness in radiation environments and high-speed performance featuring bipolar transistors (HBTs) with fT/fMAX values of up to 250/340 GHz. Besides hardening by technology, radiation-hardened-by-design (RHBD) components are used, including enclosed layout transistors (ELTs) and digital logic cells. We report design features of the ICs and the module, and provide performance data from post-layout simulations. We present radiation evaluation data on analog devices and digital cells, which indicate that the transceiver ICs will reliably operate at typical total ionizing dose (TID) levels and single event latch-up thresholds found in geostationary satellites.