Virtual DC Machine (VDCM) control is a promising approach for providing inertia support in DC microgrids, thus enhancing voltage stability. However, it suffers from a complex model and difficult parameter tuning. For this issue, an improved VDCM (IVDCM) control strategy is proposed, offering several advantages over the conventional VDCM (CVDCM) control. Specifically, compared to CVDCM, the voltage recovery control in IVDCM is moved after the VDCM loop, and a capacitor current feedback is adopted in the current inner loop. The improved control structure enables the IVDCM to provide more inertial power and mitigate the DC bus voltage fluctuations. Furthermore, the small-signal output impedance of the IVDCM can be simplified into a second-order model. The time-domain expressions for the DC output voltage are then derived, and the dynamic performance indices and constraints of the IVDCM are established, defining the feasible region for IVDCM control parameters. Consequently, an intuitive approach for control parameter design is achievable. Simulation and experimental results demonstrate the effectiveness of the proposed IVDCM control strategy and the associated parameter design method.

To address the issue of power quality, shunt active power filter (APF) has been installed to regulate the grid current in previous research. However, the resonance risk exists due to the interactions among grid impedance, APF and compensated load. Though existing methods offer solutions, their reliance on fixed models compromises the performance in dynamic scenarios. The effectiveness of active damper remains unrevealed, which is typically installed externally for dynamic suppression. Therefore, this paper analyzes the system characteristics of APF system and reveals the impedance modification effect of APF on the compensated loads. Further, the oscillation mechanism of APF system is analyzed. Ob this basis, stabilization effect of active dampers in different locations is investigated. When the active damper is installed in the scope of APF’s harmonic compensation, the negative resistor emulating strategy is proposed to replace traditional positive emulating strategy. The proposed strategy could deal with the modification effect of APF properly and stabilize the system with less power loss. Besides, the harmonic emission of active damper can be compensated by the APF, guaranteeing the power quality. Simulations and experiments are performed to verify the resonance analysis and proposed strategy.

Gallium nitride (GaN) power devices, with their high-frequency operation, low power dissipation, and high efficiency, contribute significantly to the design of electric vehicle power supply by enhancing performance and reducing weight. Nevertheless, the cascode configuration presents a limitation for GaN-based power converters: interactions with parasitic elements in the gate driver and power loop can cause significant switching overshoot and oscillations, which may leads to false turn-on and potential device breakdown of low-voltage Si MOSFET. An comprehensive analytical model of switching process considering gate driverparameters, coupling of parasitic inductance, nonlinear junction capacitance and transconductance characteristics is proposed in this paper. the influence of power loop parameters and gate drive loop parameters on transient switching behavior is investigated from perspective of switching speed, voltage and current overshoot, etc. Guidelines to make the best of cascode GaN devices are given.

The traditional hybrid distribution transformer (HDT), comprising a three-phase main transformer and power electronic converters, is widely used to address voltage sag and reactive loads in distribution networks. However, its compensation performance is constrained by the limited capacity of the converters. In scenarios involving severe voltage sags or excessive reactive loads, the HDT may fail to provide complete compensation. To address this limitation, this article introduces a reconstructable hybrid distribution transformer (REC-HDT) with multiple operating modes, designed to enhance current and voltage compensation capabilities without significantly increasing costs. The topology and three operating modes of the REC-HDT are meticulously designed and analyzed. The compensation mechanisms for voltage and current are elucidated through a detailed examination of power flow between the converter and the transformer. Furthermore, an enhanced control strategy is proposed to support smooth mode transitions across various operating conditions. Simulation studies and experimental validation demonstrate the feasibility and effectiveness of the REC-HDT topology and control strategy.

With widespread proliferation of power electronic devices, harmonic pollution has become increasingly severe in power distribution network. Owing to its simple structure and high compensation accuracy, source-current-detected active power filter (APF) has been employed for harmonic cancellation. This type of APF generates the current reference through closed-loop control scheme without sensing the load current. However, this operational principle renders conventional current-limiting strategies, such as reference truncated limiting, impractical. Because they will destroy the inner closed-loop relationship. Effective residual capacity utilization can not be achieved while maintaining fast response. Therefore, this article proposes an improved fast current-limiting strategy for source-current-detected APF. By output current feedforward, closed-loop relationship is modified to achieve partial compensation. Further, this article optimizes multifrequency feedforward coefficients for different cases. Fast-limiting control and total harmonic distortion optimization control are integrated in a cascade to form a hybrid strategy, which exhibits a more balanced performance. By instantaneous current triggering, the proposed strategy substantially reduces the response time and overcurrent risk. On this basis, available capacity of APF is better utilized. Finally, the proposed strategy is verified by simulations and experiments in which a 2.2-kW load is compensated.

The conventional overcurrent protection fails to isolate the permanent short-circuit fault with the power electronic converters interface, hindering the utilization of various converters for power supply restoration. A novel protection scheme based on the harmonic undervoltage is proposed in this paper to realize accurate and rapid fault isolation. From the system-level perspective, a three-stage harmonic undervoltage protection method is proposed, comprising instantaneous, time-delayed, and inverse-time harmonic undervoltage protection, enabling coordinated operation between primary and backup protection. The operation principle, parameter design, and extension scheme for complex networks of this novel protection method are introduced, enhancing the computational efficiency and adaptability. From the converter-level perspective, the transient overcurrent limited strategy based on voltage feedforward dynamic gain adjustment is presented for avoiding undesired device shutdown during faults. Besides, the active harmonic injection loop is added to the control system, assisting the operation of the proposed protection method. The simulation and the experimental results indicate that the above method can rapidly locate various short-circuit faults in networks with converters, facilitating flexible control of the distribution networks.

In dc microgrids (DCMGs), the insufficient inertia due to the fast-response nature of power electronic converters poses significant challenges to the dc bus voltage stability. Inertia droop control (IDC) offers a solution by emulating virtual inertia through droop-coefficient modification. However, it suffers from steady-state voltage drop and lacks a comprehensive investigation into the multiconverter scenarios. To this end, this article proposes an enhanced IDC strategy that systematically addresses the key challenges in applications to multiconverter DCMGs, including the steady-state and transient current sharing, dynamic stability improvement, and plug-and-play capability. First, a decentralized secondary voltage controller is introduced to eliminate steady-state voltage deviations. Then, a small-signal impedance model is developed to reveal the inertia enhancement mechanism and current-sharing behavior. Based on a reduced-order equivalent single-converter model, an intuitive parameter design method is proposed to determine appropriate IDC control gains within a parameter feasible region that ensures the improved dynamic performance. Moreover, a short-term small-ac-signal injection method is proposed to realize the synchronization of decentralized secondary controllers during converter plug-in, eliminating the circulating currents with no communication line required. The experiment results validate the proposed control framework and the impedance-based analysis.

The dc-link capacitors in back-to-back (BTB) converters perform as a necessary dc-link voltage supporter and power buffer for both sides. However, the dc-link capacitor is normally over-designed due to performance considerations, causing a larger volume and higher cost. This article proposes a more comprehensive and accurate design scheme of the dc-link capacitance for the BTB three-level neutral-point-clamped (NPC) converter, achieving the dc bus lightweight design. Multidimensional aspects are considered when quantifying the capacitance constraints, including small-signal interactive stability, dc-link voltage fluctuation facing a given power step change from both ac sides, and switching ripple filtering performances. Corresponding to the above multidimensional aspects, the stability constraint, response speed constraint, and filtering performance constraint of the dc-link capacitance and the control parameter value are analyzed. In addition, the active capacitor is adopted to suppress the NP voltage low-frequency oscillation and to avoid the unfavorable boundary reduction of the dc-link capacitance selection. The effectiveness of the proposed lightweight dc-link capacitance design scheme is validated through simulations and experimental results. The experimental results indicate that the dc-link capacitance of each converter can be reduced to 10 & micro;F in the 2-kW experimental BTB converter, realizing over 60% volume reduction of the dc bus compared with conventional designs

In a multi-parallel inverter system, wideband resonance is frequently induced by the interactions among inverters. On this basis, varying grid impedance will shift original resonance frequency, rendering pre-designed damping methods ineffective. To dynamically suppress the harmonic amplification, active damper has been proposed, which emulates a frequency-dependent virtual resistor. However, its damping range is restricted by control delay. Complicated compensation unit is typically required. Besides, resistance value fails to accommodate different resonance states, either. In some cases, harmonic distortion is aggravated conversely. To address these issues, this article proposes an adaptive damping strategy for active damper based on interharmonic power. In view of power flow, resonance characteristics are investigated. Direct interharmonic active power absorption is verified to be effective in both resonance suppression and harmonic elimination. On this basis, an adaptive power output mechanism is developed, which strikes the balance between damping effect and harmonic anti-interference. Besides, available damping frequency region is expanded by interharmonic reactive power closed-loop control. They collectively enhance the dynamic adaptability of existing active damper, making it more suitable for industrial applications. The detailed parameter tuning and stability analysis are presented. Experiment results validate proposed strategy under various operating conditions.

In the low-voltage distribution network (LVDN), the large-scale integration of single-phase load and new energy leads to continuous three-phase voltage unbalance. Phase switch devices (PSDs) and static var generators (SVGs) are two effective devices for voltage unbalance mitigation. However, few studies have reported that via SVGs and PSDs together to reduce the unbalance of LVDN. In this paper, a coordinated optimization strategy integrating PSDs and SVGs is proposed based on the non-dominated sorting genetic algorithm II, aiming to mitigate voltage unbalance in the LVDN. The strategy simultaneously optimizes the phase sequence and the SVG compensation current to achieve a trade-off between the three objectives: minimizing the average voltage unbalance factor (VUF), reducing phase-switching times, and minimizing the total SVG output capacity. Simulation results on an IEEE-18 node system show that the proposed method can effectively mitigate multi-node voltage unbalance while reducing both PSD switching operations and SVG capacity occupation, which demonstrate that the optimization approach effectively enhances voltage balance and operational efficiency.

This paper presents a transient stator current filtering (TSCF) method by a static synchronous compensator (STATCOM) to suppress subsynchronous torsional oscillations. Using the modal series method, the shaft torques can be derived. The analysis shows that TSCF can enable the subsychrnous modes to oscillate with minimal, constant amplitude during the transient period. Finally, a time-domain simulation was conducted to validate the effectiveness of TSCF in the IEEE First Benchmark Model (FBM).

The software-based overcurrent capability enhancement for the grid-connected converter is essential in actual engineering applications. An optimal operation parameter determination methodology for most efficiently enhancing overcurrent capability is proposed in this article, utilizing the DC-link voltage, switching frequency, and the modulation strategy as variables. Firstly, the mechanism of the non-monotonic relationship between overcurrent capability and switching frequency/DC-link voltage is elucidated, from the perspective of the output current switching ripple and the thermal distribution. Secondly, the parallel-computable loss distribution calculation model is designed, considering the output current switching ripple, ensuring both accuracy and speed in computation. Thirdly, the optimal operation determination methodology is introduced based on the above loss distribution calculation model. Combined with the actual analysis case, the optimal DC-link voltage and the switching frequency are presented by visualizing the variation behavior of the maximum loss concerning the operation parameters. Finally, the simulation and the experimental results verity the precision of the trend of the maximum loss variation and the optimality of the selected operation parameters. Based on the verification case, an improvement of 50% in overcurrent capacity can be achieved by adopting the proposed method.

Compact and efficient inverter architectures are rapidly becoming fundamental methods for integrating photovoltaic and hybrid DC energy sources into modern electrical grids. Among the emerging candidates, the dual-input split-source inverter (DSSI) stands out as a promising topology, capable of combining two independent input sources within a split-source inverter configuration. This design ensures a continuous input current, reduces the voltage stress across the semiconductor devices, and effectively regulates the DC-link voltage. To realize the full capability of the DSSI, this study introduces a dual-type modulation strategy: the conventional Sinusoidal Pulse Width Modulation (SPWM) technique and the Simple-Boost Sinusoidal Pulse Width Modulation (SB-SPWM) method. Instead of depending on additional hardware components, the proposed modulation strategy extends the achievable voltage gain and improves output voltage regulation purely through modulation. By carefully adjusting the modulation parameters, the system attains a higher level of flexibility, stability, and efficiency for various inputs. The Experimental results confirm the advantages of the proposed method, showing that the optimized SB-SPWM achieves a superior boosting capability gain, higher efficiency, and more consistent performance compared with the traditional SPWM under different source scenarios. These experiments support the applicability of the DSSI as a single-stage power conversion solution capable of meeting the demanding performance, reliability, and efficiency requirements of next-generation renewable and hybrid energy systems.

The integration of the distributed generations (DGs) stations distorts the conventional single-phase grounding (SPG) fault localization results. Considering the flexibility of DGs, a novel SPG fault localization methodology for the neutral noneffectively grounded distribution networks (NNGDNs) is proposed in this article. In the proposed method, DGs are controlled to inject the harmonic currents to actively participate in the localization process. First, the SPG fault characteristic at the harmonic frequency is analyzed, and the measured harmonic impedance at the feeder junction (FJ) is shown to correlate with the fault distance. Subsequently, typical control strategies of the grid-following (GFL) and grid-forming (GFM) DGs under the SPG fault are modified to assist the harmonic impedance detection. Then, the coupling effect between DGs at various feeders is studied, and this coupling effect is eliminated by modifying the output impedance of the control-heterogeneous DGs in the special frequency band. Finally, the SPG fault localization can be realized through the coordination operation of the multiple control-heterogeneous DGs, and the simulation model and the hardware-in-loop (HIL) experimental results verify the effectiveness under various testing conditions.

Advanced and reliable power converter solutions are fundamental to advancing future transportation systems and facilitating the ongoing transition toward environmentally sustainable technologies. Transportation systems can employ multiple sources to improve their reliability and economic operation. Therefore, a novel dual-input multilevel inverter (MLI) configuration is proposed and designed in this article for multisource transportation applications. The proposed topology synthesizes the dual-input split-source MLI-based switching capacitor (SC-DSSMLI) units, resulting in a high voltage-boosting ratio due to its integrated boost converter stage. In addition, the layout is compact and cost-effective, leveraging a modular switched capacitor (SC) structure to produce multiple output levels without increasing the number of dc sources. Furthermore, the topology's scalability is enhanced by stacking additional SC stages. The inductor duty cycle and SC unit performance can be adjusted to achieve the desired boosting factor. A modified level-shifted pulsewidth modulation technique ensures efficient operation of the proposed SC-DSSMLI topology, eliminating the complexity of the modulation schemes or additional calculations. The SC-DSSMLI's capability to operate efficiently with single- or dual-input sources offers significant flexibility over existing dual-input topologies. The continuous input inductor current is another key feature, along with a method to mitigate inrush current, which can damage SCs. Experimental results, alongside topological comparisons and various performance criteria, are presented in the article, confirming the benefits of reduced component count and high operational efficiency. Furthermore, the article provides a comprehensive analysis of the stress experienced by all switches, along with a count of passive elements, offering a detailed comparison with other existing topologies.

The oscillation problem in dc power distribution systems (dc DPS) has long been a concern, primarily due to the negative input impedance of constant power loads (CPLs) within the low-frequency range. As the system scale expands, with elevated bus power/current, modular converter system are increasingly adopted in dc DPS. The present paper analyses the stability of a cascaded system consisting of an input-parallel output-parallel (IPOP) converter system with a Buck-type CPL, based on single-converter stability analysis. The suppression of oscillation is achieved through the implementation of a load-side parallel virtual impedance (LPVI) control strategy. Finally, simulation of a 750-400-200V cascaded dc DPS validates system instability issues and the effectiveness of the LPVI approach.

Wide-bandgap semiconductor devices, such as SiC MOSFETs, offer advantages including fast switching speed, high operating frequency, low conduction losses, and high-temperature tolerance. However, issues including bridge-leg crosstalk caused by high rate of current change, high rate of voltage change, and parasitic parameters, as well as weak short-circuit withstand capability, pose significant challenges to the design of their driver circuit. Currently, the driver design for commercial SiC MOSFETs has relatively mature solutions, but challenges still exist in the driver design for high-voltage SiC MOSFETs. Therefore, this paper focuses on the gate driver design for high-voltage SiC MOSFETs. Firstly, the bridge-leg crosstalk issue in SiC MOSFETs is analyzed. Subsequently, the principles for establishing a double-pulse test platform for high-voltage SiC MOSFETs are investigated. Finally, a gate driver circuit for a 10 kV SiC MOSFET is designed, incorporating a multi-stage isolated power supply, fiber-optic communication, desaturation detection, parallel current amplification, and bidirectional gate voltage clamping protection. Experimental validation was conducted. The experimental results demonstrate that the driver circuit enables fast switching under 5 kV conditions while maintaining stable and reliable driving functionality.

The asymmetrical CLLC resonant converter is a bidirectional isolated dc/dc converter with excellent soft-switching characteristics. However, traditional CLLC converters commonly employ symmetrical analytical methods for synchronous rectification (SR) realization and parameter design, which are not suitable for asymmetrical CLLC resonant converters. Therefore, this article proposes an accurate time-domain modeling method suitable for asymmetrical CLLC resonant converters to achieve precise SR and wide voltage regulation range parameter design. This time-domain modeling method can accurately compute converter parameters such as SR angles and voltage gain for an asymmetrical CLLC resonant converter under various operating modes. The accurate SR angle data obtained through the time-domain model guarantee that the CLLC resonant converter can achieve SR under different operating conditions. Furthermore, the proposed parameter design methodology ensures that the asymmetrical CLLC converter maintains a wide voltage regulation range while preserving favorable soft-switching characteristics. Finally, the feasibility of the proposed SR method and parameter design methodology based on the time-domain model was validated through a 2-kW CLLC resonant converter experimental test bench.

With the advancement of power electronics, power systems exhibit a “double-high” trend of highpenetration power electronics. Among them, the converters serve as the foundation for integrating multiple energy sources. However, conducting a thorough analysis of its wide-frequency characteristics presents a significant challenge. Accurate widefrequency coupling models are essential for analyzing the ability of power electronic equipment to withstand wide-frequency perturbations and determining the acceptance of new energy sources in the grid. Yet system complexity and device diversity require different modeling approaches, which makes traditional methods impractical due to their complexity. To achieve a balanced compromise between model relatability and accuracy, this paper proposes a backpropagation neural network with the embedded adaptive denoising training mechanism (EADT) method for harmonic disturbance coupling analysis in a singleconverter scenario. The approach eliminates reliance on detailed system parameters, enabling direct harmonic disturbance analysis via trained models to determine current coupling characteristics.

The increasing demand for compact, efficient, and reliable power conversion structures, especially for photovoltaics, has promoted the development of sophisticated single-stage inverter topologies such as split source inverter (SSI). In this study, improving the performance of dual input split source inverters (DSSI) is targeted at utilizing a sophisticated modulation scheme. The DSSI integrates dual input sources with a split-source inverter structure, providing continuous DC input current, reduced voltage stress, and stable DC-link voltage, which are essential requirements in such applications. The proposed control strategy uses sinusoidal pulse width modulation (SPWM) and optimized simple boost SPWM (SB-SPWM) to control the output voltage and improve the system efficiency; by implementing these modulation techniques, the system offers better control of voltage gain and, in turn, exhibits better overall control of the inverter. The proposed SB-SPWM method is validated through a set of experiments with the conventional SPWM scheme. It demonstrates the improved efficiency and reliability of the proposed approach in meeting the stringent requirements of modern power applications.