A readout integrated circuit (ROIC) for uncooled microcantilever infrared focal plane arrays (IRFPAs) based on capacitive readout is proposed. The ROIC is optimized according to noise modeling and analysis to reduce noise. An experimental chip of 16×16 FPAs readout circuit has been designed and fabricated using 0.35um CMOS technology. The measurement results showed that the power dissipation is 16.5mW from a 5V supply voltage at 50Hz frame rate, the linearity is 99.2% at the typical mode; the uniformity is larger than 97% and the equivalent noise charge (ENC) is below 150e. It is believed that the ROIC has a great potential in the applications of large-scale micro-cantilever-based uncooled IRFPAs.

A novel voltage controlled oscillator (VCO) sub-band selection circuit to achieve fast phase locked loop (PLL) calibration is presented, which reduces the calibration time by measuring the period difference directly and accomplishing an efficient search for an optimum VCO sub-band. The sub-band selection circuit was implemented in a 0.18 μm CMOS logic process with a PLL using an 8 sub-band VCO. The measured calibration time is less than 3 μs in a VCO frequency range from 600 MHz to 2 GHz. The proposed circuit consumes 0.64 mA at most.

A CMOS front-end ASIC for semiconductor radiation detectors is proposed. The ASIC comprises a charge sensitive amplifier (CSA), a gm-C type shaper, a peak detect and hold circuit (PDH), and two discriminators. The PDH and the discriminators, together with some logic circuits, provide the capability to reject trailing edge pile-up. The circuit has been designed in a 0.5 μm DPTM CMOS technology and verified by simulation. The most noise-sensitive blocks, the CSA and the shaper, have been manufactured and measured. The simulation and measurement results show that the ASIC is capable of pile-up rejection.

The authors propose an improved phased locked loop(PLL)architecture with dual control paths.The two control paths have different voltage controlled oscillator(VCO)gain.The coarse tuning path has a large VCO gain,and is used to cover operating frequency range.Having a small VCO gain,the fine tuning path determines the loop bandwidth and optimizes the jitter performance.This circuit is fabricated in a 0.18 μm CMOS logic process.The presented PLL has an output range from 600 MHz to 1.6 GHz,and exhibits good jitter characteristic.

A novel voltage controlled oscillator (VCO) sub-band selection circuit to achieve fast phase locked loop (PLL) calibration is presented, which reduces the calibration time by measuring the period difference directly and accomplishing an efficient search for an optimum VCO sub-band. The sub-band selection circuit was implemented in a 0.18 μm CMOS logic process with a PLL using an 8 sub-band VCO. The measured calibration time is less than 3 μs in a VCO frequency range from 600 MHz to 2 GHz. The proposed circuit consumes 0.64 mA at most.

A 12-bit 20MS/s low power pipelined analog-digital converter (ADC) is presented. A front-end sampling network is proposed to eliminate the need of SHA. Passive capacitor error-averaging technique (PCEA) and Opamp sharing scheme are employed to achieve high resolutions and low power and area. The drawback of conventional Opamp sharing technique is resolved with polarity inverting scheme by interchanging the polarity of input and output of Opamp during different clock phases. Simulated with 0.5um mix-signal CMOS technology, the ADC dissipates 71mw from a 5V supply, and achieves a peak SNDR of 69.8dB with a 0.5MHz full-scale sine input at 20MS/s.

A 12-bit 20MS/s cost-efficient pipelined analog-digital converter is presented. A dedicated first stage is proposed to eliminate the need of front-end SHA. Passive capacitor error-averaging technique (PCEA) and opamp sharing scheme are employed to achieve high resolutions and low power and area. The offset and 1/f noise of Opamp is reduced by interchanging the polarity of input and output of Opamp, during different clock phases. Simulated with 0.5um CMOS technology, the ADC dissipates 65mw from a 5V supply, and achieves a peak SNDR of 70.1 dB with a 1MHz full-scale sine input at 20MS/s.

This paper proposes a novel calibration technique and its application on an adaptive-bandwidth PLL. The new calibration method reduces calibration time by using an improved dual-edge phase detector to compare frequency difference directly. The maximum calibration time is less than five comparison periods. With the calibration technique and an adaptive bandwidth, the PLL can maintain optimal performance during the whole working range. The proposed circuit has been implemented in 0.18um CMOS logic process. Results show that the calibration time is less than 1.2 mu s, and the total locking time is less than 3 mu s. The PLL has good jitter performance within its operating range from 860MHz to 2.1GHz.

This paper presents a novel adaptive-bandwidth charge pump PLL with low jitter and a wide tuning range. Withan adaptive bandwidth,the proposed PLL can scale its loop dynamics proportional to the output frequency and maintainoptimal performance over its entire output range. In order to improve the jitter performance of the PLL,a matching tech-nique is employed in the charge pump,and a voltage-to-voltage converter is used to achieve a low gain VCO. The experi-mental chip was fabricated in a 0. 35μm CMOS process. The measured results show that the PLL has perfect jitter per-formance within its operating range from 200MHz to 1.1GHz.

This paper presents a low power design for a 384 × 288 infrared (IR) readout integrated circuit (ROIC). For the character of IR detector (ro ≈ 100kΩ, Iint ≈ 100nA), a novel pixel structure called quad-share buffered direct injection (QSBDI) is proposed and realized. In QSBDI,four neighbor pixels share one buffered amplifier,which creates high injection efficiency, a stable bias, good FPN performance,and low power usage. This ROIC also supports two integration modes (integration then readout and integration while readout), two selectable gains, and four window readout modes. A test 128 ×128 ROIC is designed,fabricated,and tested. The test results show that the ROIC has good linearity. The peak to peak variance of the sub array is about 10mV. The power of pixel stage is only 1mW,and the total power dissipation is 37mW at a working frequency of 4MHz.

A front-end ASlC for semiconductor radiation detectors is presented. It is composed of a Charge Sensitive Amplifier (CSA), a pulse shaper, and a Peak Detect and Hold (PDH) circuit. Poly-resistor is used as source degeneration component to reduce the noise of current source in the CSA. The ASIC has been designed in a 0.5um CMOS DPTM technology and tested with Verigy 93000. The gain (PDH excluded) is 78.5mV/fC and the Equivalent Noise Charge (ENC) with detector disconnected is 800-900e. The power dissipation without the output buffer is about 2.6mW.

A novel fully integrated CMOS readout circuit for semiconductor radiation detector with sparse readout is presented. The new sparse scheme is: when one channel is being read out, the trigger signal from other channels is delayed and then processed. Therefore, the dead time is reduced and so is the error rate. Besides sparse readout, sequential readout is also allowed, which means the analog voltages and addresses of all the channels are read out sequentially once there is a channel triggered. The circuit comprises Charge Sensitive Amplifier (CSA), pulse shaper, peak detect and hold circuit, and digital logic. A test chip of four channels designed in a 0.5 um DPTM CMOS technology has been taped out. The results of post simulation indicate that the gain is 79.3 mV/fC with a linearity of 99.92%. The power dissipation is 4 mW per channel. Theory analysis and calculation shows that the error probability is approximately 2.5%, which means a reduction of about 37% is obtained compared with the traditional scanning scheme, assuming a 16-channel system with a particle rate of 100k/s per channel.

Low power design of 128×128 IR ROIC has been introduced in this paper,including the design of pixel and column readout stage.A novel low power quad-share buffered injection(QSBDI) pixel structure has been proposed.The average power of QSBDI is 500nW and the power is saved about 30%.FPN is also reduced to the order of local threshold voltage offset.In the design of column readout stage,master and slaver structure has been adapted,where master amplifier converts charge to voltage,and slave amplifier works with standby mode to drive output bus.SPICE simulation shows the power has been reduced about 60%.

A novel low power Quad-Share Buffered Direct-Injection(QSBDI)readout circuit for large format staring ROIC is proposed.In this circuit,four pixels share one common buffer amplifier.With switches' cooperation,the circuit can achieve ITR(integrate then readout)and IWR(integrate while readout)function.With area of 30μm× 30μm,the capacitor in the pixel is about 0.9pF and 4.2pC charge storage capacity,but the power of single pixel is about 500nW.At the same time,the FPN of the pixel is reduced to order of local mismatch and independent of the format of pixel array.Those characters made QSBDI an outstanding pixel structure for large format 2-D ROIC.An experimental 128×128-pixel ROIC is designed and it will be fabricated with 0.5μm DPTM n-well CMOS process.

A 10-bit 80 MS/s two-channel time-interleaved pipeline analog-digital converter is presented. Nonlinearity and Mismatch between the channels are minimized by applying partially opamp sharing scheme. And a dedicated double-sampling SHA is employed to eliminate time skew between the channels. The converter architecture is also optimized for power dissipation by employing dynamic comparator and stage scaling down technology. Simulated with 0.5 um technology, the ADC dissipates 210 mw of power from a 5 v supply, and achieves a peak SNDR of 56 dB at 80 Ms/s.

A novel data-sparsification method for multi-channel radiation detector readout ASICs is proposed. Based on the self-triggering approach, the scheme operates as follows: when one channel is being read out, the trigger signal from other channels is delayed one or more clock cycles and then processed. In this way, the dead time, during which the circuit fails to respond to the input, is reduced and so is the error rate. A 16-channel readout ASIC has been designed in a 0.5um DPTM CMOS technology. The feasibility of this novel sparse readout method is verified by simulation. Theory analysis and calculation show that the error rate is approximately 2.5%, and is reduced by about 37% compared with the conventional scanning scheme, assuming a 16-channel system with an event rate of 100K/s per channel.

This paper presents a low jitter adaptive-bandwidth charge pump PLL with an improved passive filter. With an adaptive bandwidth, the proposed PLL maintains optimal performance over its whole operating range. In order to improve the jitter performance of the PLL, matching technique is employed in the charge pump, and a voltage-to-voltage converter is used to achieve a low gain VCO. The novel circuit has been implemented in 0.35um CMOS process. Post simulation results show that the PLL can scale its loop dynamics proportional to the operating frequency and has good jitter performance within its operating range from 100MHz to 1.1GHz.

Novel schemes for a charge sensitive amplifier (CSA) and a CR-(RC)n semi-Gaussian shaper in a fully integrated CMOS readout circuit for particle detectors are presented. The CSA is designed with poly-resistors as feedback components to reduce noise. Compared with conventional CSA, the input referred equivalent noise charge(ENC) is simulated to be reduced from 5036e to 2381e with a large detector capacitance of 150pF at the cost of 0.5V output swing loss. The CR-(RC)n semi-Gaussian shaper uses MOS transistors in the triode region in series with poly-resistors to compensate process variation without much linearity reduction.

A novel readout architecture for infrared (IR) readout integrated circuit (ROIC) is proposed. When the readout rate is 5?MHz, the power of the column readout stage has been reduced from more than 47?mW to 6.74?mW, by applying master-slave column amplifier and the technology of divided-output-bus, which reduced more than 80%. In the master-slave readout structure, master amplifiers convert the charge to voltage, which has relaxed time limit. Slave amplifiers drive the output bus and ensure the readout rate, which adopts low power standby work mode. The technology of divided-output-bus is to divide the 320 pairs of switches to 20 groups and to reduce the switches connected to the output bus, which does help to reduce power dissipation of slave amplifiers.

An improved conditional carry selection (CCS) circuit is proposed in this paper. The new circuit is compared with the conventional conditional carry selection structure for a 4-bit adder. The two circuits were simulated by SPICE under the same condition and the results show that the propagation time of carry and sum (C_3 and S_3)of 4-bit adder are reduced 34.39% and 33.95%, respectively.