For compact integration of 13.56MHz NFC functionality in mobile devices, a small planar loop antenna is a necessity. Active load modulation (ALM) is a commonly adopted technique to boost load modulation amplitude to overcome weak inductive coupling in small antennas. However, due to the challenges of phase synchronization, ALM is mainly limited to low data rate NFC applications. This paper describes the challenges of supporting NFC Very High Bit Rate (VHBR) Card Emulation Mode (PICC) in small antennas. An ultra-fast retimed phase synchronization PLL technique is proposed to overcome the technical challenges of ALM for high data rate uplink transmission. A sub-sampling ADC topology is implemented as VHBR ASK envelope demodulator. A clock extractor-based PLL provides precise synchronized continuous clock to the high speed sub-sampling ADC for accurate demodulation of all ASK envelopes with modulation index (MI) ranging from 8% to 100%.

A versatile three-stage operational amplifier with Second-stage Bypass Compensation scheme (SBC) is proposed. At high frequencies, the second stage is bypassed using a capacitive feed-forward path, reducing the amplifier to a two-stage one. Unity closed-loop gain stability is then ensured using a conventional two-stage compensation technique. Two single-ended topologies and one fully differential topology of the proposed amplifier are introduced. The proposed topologies allow operation with power-supply voltages as low as 1V and, therefore, are particularly suitable for use in low voltage, high gain designs using deep-submicron technology. Subsequently, simulation results of the single-ended and fully differential amplifiers and measurement results for two applications: (a) low-dropout regulator (LDO) and (b) low-pass filter (LPF) are presented. The applications were fabricated in UMC 65nm CMOS process.

This paper describes a 55nm, 0.6mm2 Bluetooth SoC integrated in cellular baseband. Several techniques are used to enhance co-existence performance of Bluetooth with cellular and Wi-Fi. First is the design of current-mode interfaces from LNA to complex BPF for better linearity and the additional antialiasing LPF placed before ADC for outband rejection in the RX. Second is the use of a passive voltage sampling mixer to lower out-of-band emission noise floor in TX. Moreover, only two inductors are used, one of which is a field-cancelling inductor used in VCO layout to achieve a spur-free LO signal, minimizing magnetic coupling from other parts of SoC. The TX output power is +11dBm at BDR mode and +8dBm at EDR3 mode, with 1.5-kHz frequency drift and <;6% RMS DEVM. The RX sensitivity is better than -96.5dBm and -89.2dBm for BDR and EDR3 modes respectively. The measured BT RX sensitivity is -57dBm at BDR mode while co-existing with -5dBm of Wi-Fi 54Mbps OFDM.

A 45MHz to 1002MHz direct conversion Universal TV Tuner (UTV) supports world-wide TV broadcast standards, such as ATV (NTSC, PAL, SECAM), DTV (ISDB-T, DVB-T, DVB-T2, ATSC, DTMB, DVB-C/C2), EN55020 etc. The tuner exhibits less than 5.5dB noise figure (NF), >70dB image rejection, +30dBm IIP3, +67dBm IIP2 and harmonic rejection of more than 70dB over the operating frequency range. An integrated ΣΔ PLL with a novel compact integrated loop filter locks a broadband dual-tank VCO to a 29MHz reference. The tuner occupies less than 10mm2 of silicon area in 0.18μm CMOS and consumes around 659mW from 3.3V/2.2V dual supply.

A highly integrated ultra-low-cost high-performance Bluetooth 3.0+EDR SoC is implemented in 0.11-μm digital CMOS technology. The transceiver has an integrated balun shared between TX and RX, eliminating the need for a separate T/R switch. A 4 × LO-based VCO is implemented to reduce LO pulling and to minimize TX out-of-band spurious emissions. The transmitter provides high output power of +10 and +7 dBm in BDR and EDR3 modes respectively, with 1.5-kHz frequency stability and <; 6% rms DEVM. The receiver sensitivity is -95.5, - 96.5, and -89 dBm for BDR, EDR2, and EDR3 modes respectively. Total SoC DC current consumption for continuous TX transmission at +10 dBm output power is 48 mA and for continuous RX reception at reference sensitivity level is 35 mA. Total die size is 5.7 mm 2 , of which 1.8 mm 2 is occupied by RF, analog, and PMU circuits.

A highly-integrated, ultra-low-cost Bluetooth SOC implemented in 0.11μm digital CMOS technology is disclosed. To reduce BOM count and cost, an integrated balun is designed for the transceiver front-end. A 4xLO based VCO is implemented to reduce LO pulling, and minimize TX out-of-band spurious in the direct-conversion transmitter. The transmitter provides high output power at +10dBm and +7dBm in BDR and EDR3 modes respectively, with 1.5-kHz frequency stability and <6% RMS DEVM The receiver sensitivity is better than −95.5dBm, −96.5dBm and −89dBm for BDR, EDR2 and EDR3 modes respectively. DC current consumption for continuous TX transmission at +10dBm output power is 48mA, and for continuous RX reception at reference sensitivity level is 35mA. Total die size is 5.7mm2, of which 1.8mm2 is occupied by RF, analog and PMU circuits.

A readout integrated circuit (ROIC) for uncooled microcantilever infrared focal plane arrays (IRFPAs) based on capacitive readout is proposed. The ROIC is optimized according to noise modeling and analysis to reduce noise. An experimental chip of 16×16 FPAs readout circuit has been designed and fabricated using 0.35um CMOS technology. The measurement results showed that the power dissipation is 16.5mW from a 5V supply voltage at 50Hz frame rate, the linearity is 99.2% at the typical mode; the uniformity is larger than 97% and the equivalent noise charge (ENC) is below 150e. It is believed that the ROIC has a great potential in the applications of large-scale micro-cantilever-based uncooled IRFPAs.

Design of a CMOS readout circuit for 160x120 format microcantilever infrared FPAs with snapshot integration is presented in this paper. The pixel pitch is 50μm and capacitive trans-impedance amplifier is used in pixel stage for low noise and high linearity. A 800fF storage capacitor is implemented in each pixel for snapshot imaging. The pixel OTAs are powered off during pixel signals readout phase and master-slave buffer method is employed in column readout stage and output buffer stage for low power. The 160x120 ROIC has been designed and simulated for 50Hz frame frequency with one output port. The pixel rate is 1MHz, charge handling capacity is 1.5x105 electrons, pixel linearity is as high as 99.9% and the power consumption is less than 20mw. A 16x16 experimental chip has been designed, post-simulated and manufactured with a 0.35μm CMOS DPTM technology and is being tested.

A 12-bit 20MS/s low power pipelined analog-digital converter (ADC) is presented. A front-end sampling network is proposed to eliminate the need of SHA. Passive capacitor error-averaging technique (PCEA) and Opamp sharing scheme are employed to achieve high resolutions and low power and area. The drawback of conventional Opamp sharing technique is resolved with polarity inverting scheme by interchanging the polarity of input and output of Opamp during different clock phases. Simulated with 0.5um mix-signal CMOS technology, the ADC dissipates 71mw from a 5V supply, and achieves a peak SNDR of 69.8dB with a 0.5MHz full-scale sine input at 20MS/s.

A 12-bit 20MS/s cost-efficient pipelined analog-digital converter is presented. A dedicated first stage is proposed to eliminate the need of front-end SHA. Passive capacitor error-averaging technique (PCEA) and opamp sharing scheme are employed to achieve high resolutions and low power and area. The offset and 1/f noise of Opamp is reduced by interchanging the polarity of input and output of Opamp, during different clock phases. Simulated with 0.5um CMOS technology, the ADC dissipates 65mw from a 5V supply, and achieves a peak SNDR of 70.1 dB with a 1MHz full-scale sine input at 20MS/s.

A new structure 288 × 4 CMOS time delay and integration (TDI) readout integrated circuit (ROIC) is presented in this paper. The TDI function is implemented using an integration and storage circuit array and a charge amplifier with the advantages of low power and compact layout. An experimental chip has been designed and fabricated in 0.5 ¿m double-poly-three-metal CMOS technology. Bi-directional TDI, defective element deselection and two-gain option (1.015 pC/2.03 pC) functions have been realized in the experimental chip and measurement results at liquid nitrogen temperature indicated that all functions were correct and performance satisfied the requirement of long waveform IRFPA. The readout speed of each out can reach 5 MHz and the dynamic range is 75.6 dB.

A 10-bit 80 MS/s two-channel time-interleaved pipeline analog-digital converter is presented. Nonlinearity and Mismatch between the channels are minimized by applying partially opamp sharing scheme. And a dedicated double-sampling SHA is employed to eliminate time skew between the channels. The converter architecture is also optimized for power dissipation by employing dynamic comparator and stage scaling down technology. Simulated with 0.5 um technology, the ADC dissipates 210 mw of power from a 5 v supply, and achieves a peak SNDR of 56 dB at 80 Ms/s.