In this paper, we studied silicon-on-sapphire pseudo-MOS transistors based on heterostructures with intermediate ferroelectric layers made of hafnium, aluminum and zirconium oxides. The structures were fabricated using the hydrogen-initiated transfer of silicon and oxide layers of these metals onto sapphire substrates, followed by a rapid thermal annealing in the temperature range from 700 to 900 °C. Using Raman spectroscopy with the excitation by the laser radiation with a wavelength of 532 nm, a significant shift of the LO phonon peak in the silicon film on silicon-on-sapphire structures was revealed after a hydrogen-induced film transfer. The current-voltage characteristics of the developed $\mathrm{HfO}_{2} / \mathrm{Al}_{2} \mathrm{O}_{3}$ and $\mathrm{HfO}_{2} / \mathrm{ZrO}_{2} / \mathrm{Al}_{2} \mathrm{O}_{3}$ multilayer structures in silicon-on-sapphire pseudo-MOS transistors, deposited by the PEALD method on n-type (001) silicon substrates, were measured. The electrophysical parameters of the measured silicon-on-sapphire structures were calculated by the Y-function method from the drain-gate current-voltage characteristics for electrons and holes in Si layers for different SOS structures containing $\mathbf{H f O}_{\mathbf{2}} / \mathbf{A l}_{\mathbf{2}} \mathbf{O}_{\mathbf{3}}$ and $\mathbf{H f O}_{\mathbf{2}} / \mathbf{Z r O}_{\mathbf{2}} / \mathbf{A l}_{\mathbf{2}} \mathbf{O}_{\mathbf{3}}$ layers.

A model study of the composition of the neutral and charged components of SF6 plasma is conducted in a wide range of electron concentrations. Key plasma-chemical processes that form stationary concentrations of fluorine atoms in low- and high-density plasma conditions are identified. It is shown that optimized (reduced due to inefficient reactions) kinetic schemes provide satisfactory agreement between the calculation results and experimental data from published sources.

Some results on the miniaturization of silicon-on-insulator (SOI) structures and SOI elements of integrated circuits (IC) were presented. To increase IC performance efficiency, it was necessary to increase barriers and pulling electrical fields by means of high- k dielectrics and nanoscales, which appreciably reduced the mobility of charge carriers at a decrease in the length and width of a channel. Along with an increase in leakage due to source-drain tunnel currents, this limited the physical length of a channel by 10 nm even when silicon was replaced by two-dimensional (2D) materials, such as graphene and metals dihalcogenides. Three-dimensional (3D) integration in the form of double-gate transistors with complete depletion in the SOI structures with high- k buried dielectric (h- k BOX) in the form of so-called fin transistors (FinFET) with two to four gates all around (GAA) and channels from nanowires (NW FET), nanosheets (NS FET), and nanoforks (FS FET), 2D materials, and their 3D packing made it possible to increase the number of transistors on a chip, but not their performance efficiency. The variant considered as an alternative to improve the functionality of these elements was to replace the dielectrics in capacitors and transistors with ferroelectrics and resistors with memristors to turn from binary to neuromorphic logic and, in addition, to implement the principles of radiophotonics and quantum devices and sensors with parallel processing. The dynamically adjustable threshold and polarization of gate ferroelectrics in the complementary MOS metal-oxide-semiconductor field-effect transistors (MOS FET) of heterosystems on a chip (SoC) will retain ultralow power consumption.

An implementation of a universal solid-state quantum register based on electron space states in field-defined double quantum dots (DQD possesses one electron in two adjacent tunnel bound dots) in an ultrathin semiconductor nanowire is discussed. To some extent, the structure resembles that of a field-effect transistor with multiple controlling electrodes (gates). Scalability is audible and it opens up a possibility of large-scale quantum computer fabricated by advanced silicon technology. Moreover, the structure could be developed into an ensemble quantum register where instead of single nanowire an array of them with common controlling electrodes and contacts is fabricated. This ensemble register is much more resistant against environment noise caused by phonons and stray charges due to averaging and compensation. It is crucial that an individual qubit consists of two DQDs. The basic states of that qubit correspond to symmetric state of one DQD and antisymmetric state of another, and vice versa. Then the quantum information can be encoded and processed without charge transfer between dots. The probability to find an electron in a dot constantly equals 1/2 thus the Coulomb interaction between DQDs is also constant. Although the Coulomb interaction is incessant, the strength of its action depends on mutual states of interacting DQDs (in-resonance or off-resonance). Therefore, a quantum algorithm could be effectuated via manipulation solely with steady and pulse gate potentials that reminds an operation of a digital integrated circuit. The final read-out of the register is performed after decoding into charge states of DQDs and a transmission of current through the wire.

In this work, we investigated basic properties of CF4+H2+Ar plasma relevant to atomic layer etching as well as analyzed relationships between gas-phase plasma characteristics and etching kinetics for Si and SiO2. Variable processing conditions were the CF4/H2 mixing ratio and input power. The research scheme included plasma diagnostics by Langmuir probe, optical actinometry for F and H atoms as well as 0-dimensional plasma modeling. It was shown that a growth of H2 content in a feed gas a) causes the weak disturbance of electron temperature; b) lowers densities of electrons and positive ions together with increasing plasma electronegativity; and c) sufficiently influences plasma chemistry through hydrogen-related reaction mechanisms. In the last case, the most important effects are rapidly the decreasing F atom density, the domination of HF among fluorine-containing reaction products as well as an increase in plasma polymerizing ability. It was found also that decreases in both Si and SiO2 etching rates toward H2-rich plasmas appear to be slower compared with F atom flux. As this effect contradicts with increasing polymer film thickness, the suggested reasons are the chemical activity of HF molecules and/or changes in polymer film properties resulting in its better “transparency” for etchant species.

The influence of the initial mixture composition, gas pressure and input power on electrophysical parameters and density of fluorine atoms in SF6 + Ar + He plasma produced in an inductive-type reactor at 2 MHz was investigated. The combination of plasma diagnostics by Langmuir probes and optical emission spectroscopy allowed one to determine behaviors of electrons- and ions-related plasma characteristics vs. variable operating parameters as well as to suggest mechanisms responsible for corresponding effects. In particular, it was shown that the substitution of argon by helium at constant SF6 content in a feed gas affects the electron temperature, densities of charged species and plasma electronegativity through changes in both total ionization rate and electron energy losses during their interactions with dominant neutral particles. It was found that input power produces the maximum effect on the F atom density (by similar to 9 times at w = 800-1250 W) while the influence of the Ar/He ratio and gas pressure (especially at p < 15 mtorr) appears to be much weaker. Such situation is caused by opposite trends of electron temperature and electron density that results in rather small changes in the effective frequency of SFx + e- SFx-1 + F + e reaction family. It was found that fluxes of both fluorine atoms (Gamma(F)) and positive ions (Gamma(+)) follow changes in their densities, and the minimum Gamma(F) /Gamma(+) value in He-rich plasmas corresponds to low pressures and input powers.

The mechanism of the latent track formation in the silicon-on-insulator and silicon-on-sapphire structures with the 15 nm thick buried HfO2:Al2O3 (15:1) interlayers were investigated under the irradiation with swift Xe+26 (150 MeV) and Bi+51 (670 MeV) ions. The ion fluence was 2×1011 cm-2. The silicon-on-insulator and silicon-on-sapphire structures were prepared by direct wafer bonding and subsequent hydrogen transfer of a 500 nm thick Si layer coated HfO2:Al2O3 stacks by atomic layer deposition. Structural changes in the layers after irradiation were studied using cross-sectional high-resolution transmission electron microscopy. In the high-k interlayer, the swift ion implantation produces molten ion tracks, which form bulging regions in the interlayers. Using liquid diffusivity ~10-4 cm2/s and bulging height -1-2 nm it gives the recrystallization time for HfO2:Al2O3/Si interfaces about 100-200 ps. We suggest that the bulge direction observed by cross-sectional high-resolution transmission electron microscopy should be determined by the molten density of substrate material: 9% higher in the case of silicon and 45% lower for molten alumina. The ion tracks sizes in silicon were estimated from the size of the bulging diameters. These dimensions were about 4-6 and 6-9 nm wide in the case of Xe+ and Bi+ ions, respectively. The electrical parameters of silicon-on-insulator structures were compared with the same for silicon-on-sapphire devices.

Three-dimensional integration of double-gate transistors with full depletion in silicon-on-insulator structures and a high-k buried dielectric, in the form of so-called fin field effect transistors with two to four gates (gate-all-around) and nanowires, nanosheets, nanofork transistor channels, 2D materials and 3D cross-bar architecture made it possible to increase the number of transistors on a chip, but not their performance and energy consumption. The last one is crucial for ultra large scale integration chips for artificial intelligence. As a goal and a new ULSI platform, the option of decrease in the number of transistors and increase in their functionality is considered by replacing dielectrics under their gates with ferroelectrics and resistors with ferroelectric tunnel junctions, which provide low-voltage operations, and it leads to a transition from binary to neuromorphic logic, as well as to the implementation of the principles of radiophotonics, quantum devices and sensors with parallel processing. Dynamically adjustable threshold or ferroelectric capacity, resistors with ferroelectric tunnel junctions and a ferroelectric field effect transistor in a system-on-chip can reach ultra-low power consumption for Internet-of- Things.

In this work, we investigated and compared effects of gas pressure (5-25 mTorr) and input power (800-2750 W) on plasma parameters and kinetics of active species in Ar-rich (42 % Ar + 8 % He) and He-rich (8 % Ar + 42 % He) SF6 + Ar + He inductively coupled plasmas applicable for both conventional reactive-ion and cryogenic etching purposes. The combination of plasma diagnostics (Langmuir probes, optical emission spectroscopy) with 0-dimensional plasma model allowed one a) to examine changes of electrons-and ions-related plasma parameters determining both gas-phase and heterogeneous process kinetics; b) to determine partial densities of neutral and charged species; and c) to understand differences between Ar and He in respect to their impacts on plasma chemistry. In particular, it was found that substitution of argon by helium noticeably lifts up electron temperature, lowers electron density as well as increases plasma electronegativity through changes in both total ionization rate and electron energy losses in collisions with dominant neutral particles. The mechanisms of above effects were discussed.

The investigation focuses on the development and research of plasma etching processes for the manufacturing of silicon refractive X-ray optical elements: planar compound lenses and also reflective devices - mirror interferometers. Although silicon is not the best material for refractive optics because its refractive and absorption characteristics are concede to materials made from lighter chemical elements, impressive advances in silicon technology in MEMS (micro-electromechanical systems) and nanoelectronics have made it possible to achieve record-breaking precision in the formation of structures, which concerns not only geometry but also minimal roughness. A 100-lens interferometer (with 29 lenses in each channel) was manufactured using the proposed technology. Its' focusing capabilities were investigated both numerically and experimentally, although the fringes with a width of 2.0μm turned out to be wider than the calculated ones $(0.5 \mu\mathrm{m})$; these effects should be attributed to the finite size of the radiation source. The peak-to-peak surface roughness of the lenses was measured to be approximately 20 nm, whereas RMS (root mean square) sidewall roughness measured by SEM, AFM and Optical Profiler does not exceed 2 nm/um. This level of roughness does not significantly affect the formation of interference patterns.

The filaments rupture and recovery in oxide-type memristors have been theoretically studied. The model is based on the kinetics of oxygen vacancies and includes Joule heating of the oxide medium, which enhances the diffusion and drift of oxygen vacancies in an external electric field. The current-voltage characteristic of the model structure was obtained. Comparison with experimental results allowed for the determination of the constants used in the modeling. The peculiarity of the current-voltage characteristic observed in experimental works is explained.

The mechanism of resistive switching in Pt/HfO2(8 nm)/HfOXNY(4 nm)/TiN structures, in which there are two resistive switching modes: bipolar resistive switching and complementary resistive switching. We demonstrate that resistive switching without external current compliance is possible. It is shown experimentally that the conductivity in the low-resistance state corresponds to the space-charge-limited current. A qualitative model is proposed that describes the transition from bipolar resistive switching to complementary resistive switching using Schottky barrier modulation at the metal-insulator interface. Based on this model, an explanation is given for the degradation of the low-resistance state during endurance measurements.

The electrophysical parameters of the plasma and the kinetics of plasma-chemical processes in a CF4 + H2 + Ar mixture while varying the CF4/H2 ratio are studied. When using diagnostic methods and plasma modeling together, it is found that replacing tetrafluoromethane with hydrogen (a) leads to a decrease in the plasma density and an increase in electronegativity; and (b) it causes a disproportionately sharp drop in the concentration of fluorine atoms. The reason for the latter effect is the increase in the frequency of the death of atoms in reactions of the CHFx + F → CFx + HF type initiated by heterogeneous recombination via the CFx + H → CHFx mechanism. The simultaneous increase in the concentration of polymer-forming CHxFy (x + y < 3) radicals indicates an increase in the polymerization load of the plasma on the surfaces in contact with it.

The silicon-on-sapphire (SOS) pseudo-MOSFETs with high -k buried hafnium dioxide interlayer (IL) were investigated after the hydrogen induced Si and HfO2 layer transfer on c-sapphire wafers and annealing at 600-1100 degrees C. HRTEM, GIXRD and Raman measurements were used to reveal the hafnia phases for furnace and rapid thermal annealings (FA and RTA).

The results are presented on changes in the parameters of pseudo-MOS transistors based on silicon-on-sapphire (SOS) mesastructures upon irradiation with swift heavy ions (SHIs) of Xe ^+26 (150 MeV) and Bi ^+51 (670 MeV) to a fluence of 2 × 10^11 cm ^-2 , indicating the accumulation of mechanical stresses and charges in the intermediate ferroelectric (Fe) layers of HfO _2 films (HO) with a thickness of 20 nm and Hf _0.5 Zr _0.5 O _2 (HZO) laminated with inserts of Al _2 O _3 monolayers (HA, HZA) or without them. SOS heterostructures are formed by direct bonding and hydrogen transfer of a silicon film (500 nm) with HA and HZA nanolayers pre-applied by plasma-stimulated atomic layer deposition onto sapphire. Electrophysical parameters are determined from the drain current—gate voltage characteristics ( I_ds – V_g) of pseudo-MOS transistors with tungsten drain/source electrodes (100 nm) deposited by magnetron sputtering on SOS mesastructures through a lithographic mask. Comparison of the characteristics with Raman scattering analysis showed the correspondence of the mechanical compressive stresses introduced by SHI irradiation in silicon with the ratios of the Xe and Bi track volumes in the HA ferroelectric and sapphire.

Ruthenium thin films were deposited by plasma enhanced atomic layer deposition (PEALD) using Ru(EtCp)2 and oxygen plasma on the modified silicon surface and SiO2/Si substrates. The substrate temperature has a significant impact on film growth. The GXRD and SIMS analysis have shown that at the substrate temperature T = 375°C there is a sharp change in the mechanisms of surface reactions, which leads to a change in the film composition from RuO2 at low temperatures to a pure Ru film at higher temperatures. This was confirmed by measurements of the electrical resistivity of Ru-based films. The lowest surface roughness 1.5 nm was obtained at a film thickness of 29 nm deposited at 375°C on a SiO2/Si-substrate. The measured resistivity of the Ru film was 18–19 μΩ cm. Issues regarding the plasma-chemical etching of ruthenium and the spin-on of a low-k dielectric onto arrays of lines are taken into account.

The results of a study of promising technologies for the formation of trench and planar integrated capacitors with a high specific capacitance per unit of chip surface are presented, as well as a review of the literature and achievements of leading manufacturers of integrated circuits on this topic. In particular, the results of a study of dielectrics with a high permittivity, including ternary compounds obtained by atomic layer deposition, are presented. The issues of deposition of conformal dielectric and metallic layers in high-aspect trench structures in silicon are studied in details. The results of implementation of the novel cyclic process of deep silicon ething (nitridisation-etching) is presented. The results obtained can be used to implement industrial technological routes for the formation of integrated capacitors.

One promising approach to increase the capacity density of integral microcapacitors, microsupercapacitors, and microbatteries is three-dimensional structure design, where electrodes are exposed in three dimensions instead of conventional in-plane electrodes. Such structures include nanowires, nanotubes, nanopillars, nanoholes, nanosheets, and nanowalls. In this work, a cryogenic silicon etching process suitable for fabrication of structures with high electrode area is proposed. A numeric model of this process is experimentally calibrated and used for pillar array structure sidewall area optimization. The use of adaptive Runge-Kutta-Fehlberg time integrator allows to achieve almost linear overall computation complexity as a function of simulated etching time, despite the linear increase in conductance computation complexity with depth. A rule for choosing optimal geometric structure parameters under technological constraints is formulated. An optimized trefoil-like structure is proposed, resulting in a total 5.5% increase in sidewall area with respect to the hexagonal array of circular pillars, resulting in 20.33 sidewall area per unit chip area for 30 min long etch or 31.80 for 60 min long etch.