Large-span suspended silicon-on-insulator (SOI) microelectromechanical systems (MEMS) structures are increasingly used in millimeter-wave and sub-terahertz (sub-THz) waveguide switching. However, their fabrication is challenged by residual stress arising from metallization layers essential for electromagnetic wave transmission. In sub-THz MEMS switching circuits operating below 200 GHz, the increased waveguide cross-sections demand exceptionally long MEMS-actuated structures with extreme span-to-thickness ratios, making them highly susceptible to severe out-of-plane deformation from metallization. This work investigates stress relaxation and controlled stress-gradient inversion in an 800- nm sputtered gold film deposited on a 4.95-mm-long, 30-μm-thick suspended SOI MEMS structure. Gold deposition introduces a compressive stress gradient of approximately −475MPa/mm, producing a 2.7μm downward deflection that inhibits switching operation. Systematic post-deposition annealing experiments from 50 °C to 250 °C revealed that while low-temperature treatments provide negligible relief, a treatment of 250 °C for 2 h effectively relaxes the film stress. This process results in a stable transition to a mildly tensile stress gradient of 35.2MPa/mm, restoring structural flatness. The method is validated using a 163–183 GHz MEMS waveguide crossover switch, which serves as a representative example of large-span SOI MEMS reconfigurable surfaces driven by MEMS actuators. RF characterization of the device confirms restoration of switching functionality. These results demonstrate that post-deposition annealing is an effective process for controlling metallization-induced residual stress in large-span SOI MEMS structures, enabling broader exploration of large-scale SOI MEMS device architectures, including millimeter-scale actuators, extreme-span reconfigurable surfaces, and large-area resonant structures.
In this work, a novel staggered-gate complementary field-effect transistor (SG-CFET) is proposed to overcome the severe back-end-of-line (BEOL) routing congestion and contact self-blocking issues in conventional CFET designs. The SG-CFET features unique split and staggered gate configuration, which effectively eliminates the requirement for high-aspect-ratio vias and mitigates vertical spatial crowding. The SG-CFET also enables a unique design of SRAM layout that resolving Q-QB spatial conflicts, thereby reducing the standard 6 T-SRAM layout area by 30.26%. The DTCO framework indicate that the optimized routing design effectively reduces critical parasitic RC, achieving 44.14% and 66.31% reductions in storage node (Q-QB) and word-line (Q-WL) coupling capacitances, respectively. Without compromising the static noise margins, the SG-CFET SRAM exhibits significant dynamic performance enhancements, decreasing read and write delays by 8.80% and 16.63%, and the corresponding energy-delay products (EDP) by 22.54% and 30.36%, respectively. These results fully validate the SG-CFET as a highly promising architecture for continuous area scaling and high-performance digital circuit applications.
Two-dimensional van der Waals ferroionic materials have attracted increasing attention for low-power memory and neuromorphic devices owing to the coupled characteristics of tunable polarization ordering and ionic migration. However, the role of ion migration and redistribution in resistive switching processes remains insufficiently understood. Here, we construct a Gr/CuBiP2Se6 (CBPS)/Cu memristor based on the twodimensional layered antiferroelectric material CBPS as the switching layer. The device exhibits forming-free nonvolatile resistive switching with a low set voltage of 0.8 V, an on/off ratio of 104, and a retention time of 104 s. Moreover, the device can be reconfigured between volatile threshold switching and nonvolatile resistive switching by regulating the compliance current. Systematic comparative analysis reveals that the resistive switching behavior differs from the electrochemical metallization conductive filament mechanism, but instead originates from the formation of conductive pathways driven by migration of Cu ions within the CBPS layer. This work highlights the critical role of ion migration in resistance-state modulation of two-dimensional ferroionic materials and suggests CBPS as a promising candidate for multifunctional and high-performance neuromorphic devices.
This manuscript presents a dual-band Voltage-Controlled Oscillator (VCO) design with temperature resistance circuit. It employs two Temperature Resistant VCOs (TRVCOs) that can operate from 350 MHz to 2.4 GHz and 2 GHz to 6.29 GHz. A temperature resistant circuit (TRC) is used to convert the temperature variation to frequency which can be used as one of the features for estimation of aging effect of the circuit using machine learning model. Three models -linear regression, polynomial regression (2nd degree) and random forest are considered and trained using synthetic data and random forest outperformed the other two in terms of mean absolute error. The variation of the frequency is controlled up to 260 MHz at 1500 degrees C, making it useful for use even in harsh environment. The design is implemented in cadence 90 nm gpdk CMOS Technology.
