The penalty associated with data cache misses is one of the obstacles to the performance of SMT trace processors. The increased latency is not only required to resolve the missing data, the miss will also have negative impact on the PE resources utilization rate of the SMT trace processors. When data cache miss occurs in SMT trace processors, all the completed traces following the data-miss-trace (a trace with at least one data cache miss) will be delayed to commit for the data cache miss event. PE resources occupied by those traces can not be released until traces are committed, which wastes the PE execution resources and hampers the performance of SMT trace processors.In this paper, we propose several data cache miss sensitive thread scheduling mechanisms with the aim to tolerate the penalties of data cache misses. By choosing the thread wisely in trace dispatch and trace commit stages, the SMT trace processors performance can be improved further. Simulation results show that when using L1-L2 thread scheduling mechanism, performance will be improved by 2.8% (2-thread SMT trace processors), 8.0% (4-thread SMT trace processors) and 18.2% (8-thread SMT trace processors) with 8-PE. 512 KB L2 cache configuration. (C) 2006 Elsevier B.V. All rights reserved.

In order to catch the events that satisfy the given importance among the relative frequent events,RFAI is proposed,which first gathers the relative frequent events and puts them in buffers and then marks them with the given importance.Making use of such events in the Run-time optimization can gain better optimization value and higher stability.

Trace Processors is a promising next-generation microarchitecture that exploits implicit thread-level parallelism (TLP) in conventional applications by employing aggressive control and data speculation techniques. Although high performance can be achieved by trace processors, but in fact, processing element (PE) resources are still underutilized due to frequent trace cache misses and next-trace mispeculations. When trace cache miss occurs, trace dispatch engine must stall and supply nothing to idle PE until the completion of trace construction. When next-trace mispeculation occurs, in addition to trace dispatch engine stall, all speculative execution results after the mispeculated trace must be discarded. All the operations on those squashed traces are useless. When trace processors scales up with more PEs, this problem will become more severe.Addressing to this problem, we propose augmenting multiple thread contexts into trace processors. A combined microarchitecture-Simultaneous Multithreading trace processors (SMT trace processors) is proposed in this paper. By dispatching trace from other threads, the penalties of trace cache miss and next-trace mispeculation can be tolerated. Introducing multiple thread contexts reduce the percentage of wrong-path speculations for each thread and improve PE execution efficiency significantly. Simulation results show that integrating two thread contexts can improve 8-PE trace processors performance 27.7%. When augmenting four and eight thread contexts, the corresponding improvements are 28.7 and 15.4%. And we believe that even higher performance improvement can be expected when we integrate more PEs into SMT trace processors. (c) 2005 Elsevier B.V. All rights reserved.

The idea of two-level Trace Cache is proposed which provide a second-level trace cache that captures replaced traces from first-level trace cache due to capacity conflict,to partly lighten this problem and improve processor performance. Accordingly,the access pressure of instruction cache is alleviated and such a free resource can be used in others aspects,such as trace preconstruction.Results show that for big-work-set programs,such as go and gcc,adding 1MB second-level trace cache to 64KB first-level trace cache increases processor performance by 13% and reduces access pressure of instruction cache by 27%.

Trace preconstruction mechanism proposed in this paper observes the instruction stream, and marks the frequent miss trace andconstructs a set of traces using the instruction fetched from the conventional instruction cache in advance of when they are needed. Path-based tracepreconstruction tracks the execution history of the traces, when predicting the next trace to be fetched, it also predicts the next nth trace and decidesweather it should be pre-constructed or not. Constructing these traces before using them, the trace cache miss rate is reduced significantly.

The performance of trace processor rests with trace cache efficiency to a great extent. Higher trace cache miss rate will reduce performance significantly because no traces can be dispatched to the back-end PEs when trace cache miss occurs until the completion of missing trace construction. When running large work set application, higher capacity miss rate is inevitable for the relatively small capacity of trace cache. With the ever-increasing conventional application scale, this problem will become more severe.Addressing to the high capacity miss rate, a two-level trace cache is incorporated with conventional one-level trace cache in this paper. We found that augmenting two-level trace cache can only improve performance in a limited way for the long access latency of two-level trace cache. In order to reduce the access latency of two-level trace cache, a path-based next N trace prefetch mechanism is proposed in this paper. Path-based next N trace prefetch mechanism prefetches the next N trace from current running trace with the help of path-based next N trace prediction which is an extension to the path-based next trace predictor. Simulation results show that the path-based next N trace prefetch mechanism with prefetch distance three attains 11.3% performance improvement over the conventional one-level trace cache mechanism for eight SPECint95 benchmarks. (C) 2004 Elsevier B.V. All rights reserved.

In this paper, we propose a new next generation high-performance micro-architecture based on the combination of simultaneous multithreading and trace processor. By exploiting both Instruction-Level Parallelism and Thread-Level Parallelism, Simultaneous Multithreading Trace Processor can be expected to achieve higher performance than SMT or Trace Processor individual. We describe the organization of SMT Trace Processor architecture and some fundamental techniques. A path-based multiple traces prediction mechanism is also described in the paper.