In this paper, a co-processor centric multilayer runtime library (CellLib) was proposed by extending memory access library and enhancing the co-processor's independency. The library supports both MPI and release-consistency-based Pthread programming model. The structure of multilayer runtime library and the flexibly extended memory access library not only make the model more efficient and scalable but also enhance the performance of irregular applications. In the model, while MPI programming interface enables large exiting MPI applications to be ported to the CBEA easily and facilitates the traditional parallel programming, the release-consistency-based Pthread programming interface offers an efficient task runtime library to both MPI and the system-level users who need full control over the architecture. The experimental results show that the proposed multilayer runtime library is suitable for various applications and can achieve better performance by using a profile based on optimizing technology built in memory access library. (C) 2011 Published by Elsevier Ltd. Selection and/or peer-review under responsibility of the Organizers of 2011 International Conference on Energy and Environmental Science.

基于Cell处理器的异构多核架构及软件显式管理的多级存储层次,使其面临编程困难和性能难以有效发挥等问题.现有基于Cell/B.E.的编程模型多侧重于支持类似于流处理的"批量访存"(bulk data transfer)应用,传统非规则访存应用性能较低.通过扩展Cell/B.E.访存库增强协处理单元的自主作用,以协处理单元为中心建立Cell计算平台上的MPI和弱一致性Pthread分层并行编程运行时支持.分层的运行时支持结构及扩展后的Cell/B.E.访存库使模型具有更好的效率和可扩展性,并且提高了非规则应用的性能;模型中的MPI方便了大量传统并行应用向新架构的移植及开发,而弱一致性Pthread则为MPI提供高效的任务运行时管理支持及为系统级用户提供对架构全面控制的编程接口.实验结果表明,提出的运行时支持技术不仅可适应不同应用的要求,同时借助访存库中的剖分优化机制可有效地挖掘Cell/B.E.架构性能.

Function calls in threads adopt the shared stack model in speculative multithreading based on Chip Multi-Processor.A separate stack model is presented to eliminate the locking problem in the shared stack model,in which one core is associated with one stack on a one-to-one basis and the cooperation of those stacks supports the function calls in speculative multithreading.The stack memory management is achieved by means of adding two instructions to the speculative multithreading simulator so that the locking problem can be effectively eliminated.The compiler is modified to generate appropriate code to ensure the semantic correctness of the program,and the two instructions,get and update,are added to the simulator that supports speculative multithreading to manage the corresponding stack memory.Since the locking problem in the separate stack model is eliminated,the number of determinate threads spawned increases in various degrees and the parallel speedup of the program is increased.Experimental results show that the average speedup of the Olden benchmark suite is increased by 3.85%.However,since factors that affect the parallel speedup are complex,there are some cases that the parallel speedup decreases in the separate stack model.

In Speculative Multithreading, data dependence that limits the speedup of speculative parallelization needs to be resolved to achieve a high performance. This paper designs a synchronization execution model, with the support of compiler, to synchronize store and load instructions that frequently have data dependence on each other. We use hardware profiler to gather dependence violation information of memory data, and the profiler information is fed back to the compiler. The compiler analyzes the synchronization efficiency, select store/load pairs of great synchronization potential, and inserts synchronization instructions using insertion algorithm. Loop threads and non-loop threads can both be synchronized. The hardware support is also given in the paper. The experimental results show that the synchronization under the compiler support can effectively resolve some memory data dependence and improve the performance of the speculative execution.

Speculative multi-threading(SpMT)is an effective approach to exploit thread level parallelism of irregular programs based on co-design of hardware and software.SpMT compilers generate SpMT target code from sequential source codes,and give acceleration on multi-core architecture with the support of special SpMT execution model.A superscalar pipeline structure for SpMT execution model and a runtime memory management approach,named independent stack,is presented for hardware platform to effectively support empirical study and performance evaluation of SpMT programs.The implementation of Prophet Simulator is extended and is evaluated using Olden benchmark.Results show that the extended Prophet improves the accuracy and flexibility,while maintains the performance of Prophet.

Most programming models for CBEA(Cell Broadband Engine Architecture) well support bulk data transfer application which is suitable for stream processing,but the applications whose memory access patterns are irregular or unpredictable can not be supported or suffer performance degradation.This paper proposes a MPI programming model and corresponding runtime library to support both streaming and irregular applications.The MPI communication was assigned on PPE(PowerPC Processing Element) side to broaden the applicable field of the model.Moreover,a runtime memory access profiling infrastructure under uniform access interface was adopted in the model to help programmer to select proper memory access method and optimize data transfer between different memory hierarchies.The experimental results show that,besides getting high speedup ratio and supporting various memory methods,the application based on proposed parallel programming model performs about 30%~50% better than that based on related technologies.

A memory access technology is proposed to solve the problems of programming and performance caused by explicit management for multi-level memory hierarchies of Cell broadband engine architecture(CBEA).The access to main memory on CBEA is classified into two major types: bulk data transfer and on-demand data transfer.For bulk data transfer,the overhead of on-chip memory access is reduced by proper organization of data buffer.Meanwhile,a software-managed cache supporting coarse-grained access and data pre-fetch are adopted to enhance the performance of on-demand off-chip data transfer.In order to facilitate programming,a memory access library based on the proposed methods is implemented.Experimental results show that the performance of applications based on the proposed bulk data transfer technology is about 30%-50% higher than that of applications based on ALF and CellSs.For on-demand data transfer,the proposed software-managed cache performs about 20%-30% better than that of CBE SDK does,and the data prefetch technology based on four-buffer gets about 50% performance increase compared to single-buffer cache.

Speculative Multithreading (SpMT) is an effective mechanism for parallelizing irregular programs which are hard by conventional approaches. SpMT technology can be applied to exploit Thread-Level Parallelism effectively through allowing multiple threads executed in the presence of ambiguous data and control dependences while the correctness of the programs maintained by hardware support. This paper focuses on the thread partitioning method for Prophet, a SpMT compiler system. The thread partitioning method is based on the weighted control flow graph (WCFG) of the procedure. A structural analysis and some heuristic rules are used to partition the WCFG into sub-graphs and each sub-graph represents a candidate thread. The inter-thread data dependences are predicted by pre-computation slice to reduce RAW violation. The thread partitioning method proposed in this paper deals with both loop region and non-loop region partitioning for the consideration of general purpose programs partitioning. Experimental results show that an average speedup of 30% can be achieved by our thread partitioning method.

While the CBEA (Cell Broadband Engine Architecture) offers substantial computational power, its explicit multilevel memory hierarchy poses significant challenges to traditional programming, especially in performance and programmability. Software-managed cache is a technique that attempts to address such issues. But there still remain some limitations in current software-managed cache technologies. First, a complex managing logic of the full implementation of the software-managed cache which is not suitable for SPU designed as a vector computational unit influences computation significantly. Second, the external managing code of the software-managed cache causes the amount of computing code explosion. Besides increasing the computing burden of the accelerator, the external code occupies precious room of local storage which is shared by computing code and data. Finally, its inconvenient user interface presents significant obstacles for it to be widely applied. Based on the locality of memory access, this paper proposes an efficient software-managed cache named ECellS cache. In the paper, several customized library interfaces were designed respectively to simplify the cache implementation and reduce cache code size. On the other hand, the code segment of the application which accesses data residing in main memory frequently is defined as a cache section. Several of these types of cache sections could be combined into a cache bind and be managed in parallel by using SIMD technology. By this type of coarse-grain managing method and additional simplifying the construction of software cache, ECellS cache reduces both the burden of SPU to manage the cache buffer and the size of the cache managing code. Finally, based on local address remapping technology, a more convenient programming interface which is similar to OpenMP directive is presented to facilitate programming. By this technology, requesting for data residing in the main memory will be automatically mapped to cache buffer in local storage of SPE, and there needs to be no extra modifying for the computing source code inside the cache section except for inserting the directive outside of it. Experimental results of this paper based on the Cell processor demonstrate that our proposed software-managed cache improves performance by 15-35% over the CBE SDK software-managed cache in most test cases. With ECellS cache it could be more convenient for the user to develop and port applications based on CBE architecture.

In the paper, we investigate the memory access technology on cell broadband engine architecture (CBEA), and develop a profiling infrastructure for memory management on the architecture. By registering the dynamic memory allocation and providing details of trace of memory access, the infrastructure provides the data partition information automatically which alleviates the burdens of programmer and provides a safety guarantee for aggressive data prefetch for computing task. On the other hand, the profile information is useful for analyzing the patterns of memory access and helpful for further performance optimization. Experimental results show that applications implemented based on our SDK library not only support aggressive memory access method without the requirement of external data partition information, but also could be optimized aggressively under the guideline of the profile information provided by the proposed SDK library.