Modern graphics processing units (GPUs) exhibit increasing demands for register files (RFs) with larger capacity and bank sizes, which jeopardize the traditional SRAM-based RF designs due to their large die area and long access latency. Recent hybrid RF designs, e.g., SRAM and spin-transfer torque random access memory (STT-RAM)-based RFs, mitigate the issue by exploiting the density and performance advantages in STT-RAM and SRAM, respectively. However, existing hybrid RF designs adopt coarse integration that has limited write bandwidth between SRAM and STT-RAM, which restricts the adoption of different warp schedulers at runtime. In this article, we propose FRF, a warp-scheduler friendly fine-grained hybrid RF design using SRAM/STT-RAM hybrid cell (HC) structures. By integrating one SRAM cell and $N$ STT-RAM cells as one HC, FRF exploits internal write paths to enlarge the access bandwidth between SRAM and STT-RAM and thus greatly optimizes the area and performance. FRF enables the concurrent context-switching such that different warp schedulers may be adopted at runtime. FRF adopts interleaved register mapping (IRM) and on-demand register remapping to further improve the utilization of SRAM in each HC. Our experimental results show that, on average, FRF achieves 50% performance improvement and 40% energy consumption reduction over the coarse-grained hybrid design when adopting loose round-robin (LRR), and achieves 159% efficiency improvement over pure STT-RAM-based RF.

PIM (Processing-in-memory)-based CNN (Convolutional neural network) accelerators leverage the characteristics of basic memory cells to enable simple logic and arithmetic operations so that the bandwidth constraint can be effectively alleviated. However, it remains a major challenge to support multiplication operations efficiently on PIM accelerators, in particular, DRAM-based PIM accelerators. This has prevented PIM-based accelerators from being immediately adopted for accurate CNN inference.In this paper, we propose LAcc, a DRAM-based PI M accelerator to support LUT-(lookup table) based fast and accurate multiplication. By enabling LUT based vector multiplication in DRAM, LAcc effectively decreases LUT size and improve its reuse. LAcc further adopts a hybrid mapping of weights and inputs to improve the hardware utilization rate. LAcc achieves 95 FPS at 5.3 W for Alexnet and 6.3× efficiency improvement over the state-of-the-art.

Multivariate Gaussian distribution random numbers are widely used in the field of machine learning and financial engineering computation. Based on the Fast Jump Ahead algorithm, a parallel hardware acceleration architecture for generating multivariable Gaussian vectors is proposed in this paper. The structure uses WELL19937 algorithm as the basic uniformly distributed random number generator and is capable of generating arbitrary number of parallel uncorrelated multivariate Gaussian vector sequences. The experimental results show that the parallel acceleration structure with P parallelism can achieve the throughput of generating P / N random vectors per cycle for dimension N, which is superior to the related work and the implementation of CPU and GPU.

In this paper, a software/hardware framework is proposed for generating uniform random numbers in parallel. Using the Fast Jump Ahead technique, the software can produce initial states for each generator to guarantee independence of different sub-streams. With support from the software, the hardware structure can be easily constructed by simply replicating the single generator. We apply the framework to parallelize MT19937 algorithm. Experimental results shows that our framework is capable of generating arbitrary number of independent parallel random sequences while obtaining speedup roughly proportional to the number of parallel cores. Meanwhile, our framework is superior to those existing architectures reported in the literatures in both throughput rate and scalability. Furthermore, we implement 149 parallel instances of MT19937 generators on a Xilinx Virtex-5 FPGA device. It achieves the throughput of 42.61M samples/s. Compared to CPU and GPU implementations, the throughput is 10.0 and 2.5 times faster, while the throughputpower efficiency achieves 167.3 and 18.1 times speedup, respectively.

Modern Convolutional Neural Networks (CNNs) are computation and memory intensive. Thus it is crucial to develop hardware accelerators to achieve high performance as well as power/energy-efficiency on resource limited embedded systems. DRAM-based CNN accelerators exhibit great potentials but face inference accuracy and area overhead challenges.In this paper, we propose DrAcc, a novel DRAM-based processing-in-memory CNN accelerator. DrAcc achieves high inference accuracy by implementing a ternary weight network using in-DRAM bit operation with simple enhancements. The data partition and mapping strategies can be flexibly configured for the best trade-off among performance, power and energy consumption, and DRAM data reuse factors. Our experimental results show that DrAcc achieves 84.8 FPS (frame per second) at 2W and 2.9× power efficiency improvement over the process-near-memory design.

Convolutional neural network (CNN) extracts features from big data by using the multilayer network structure. Due to the high effectiveness, CNN has achieved great successes in many fields such as computer vision and speech analysis. However, CNN training is quite challenging because computing the gradients through multiple layers is time consuming. In this paper, we propose to accelerate the computation of gradients in the convolutional layer by CPU+MIC heterogeneous computing technique. In particular, we evaluate the time costs of computing the gradients of all layers in the Caffe framework, and found that the convolutional layer occupies the overall computational overheads. Based on this observation, we implement the intensive matrix manipulations of convolutional layers on the MIC coprocessor with OpenMP in the Caffe framework. To fully utilize the threads provided by MIC, we set two types of threads including data threads and MKL threads, and give a thread setting strategy with both theoretical and empirical analysis. We evaluate our acceleration method on several typical CNN models on the ImageNet dataset, and show that it speedups the computation of convolutional layer by about 6.8 times, and speedups the computation of overall training by about 5.8 times compared with those performed on single CPU.

Deep neural network (DNN) learns hierarchical representations from big data in a multilayer network structure and has achieved great successes in many fields such as computer vision and speech analysis. Since DNN usually contains several billions of parameters, the asynchronous stochastic gradient descent (ASGD) algorithm is often used to train an effective DNN model on a computer cluster. However, as the increase of computing nodes and data size, ASGD suffers from serious slow convergence deficiency because the parameters might be wrongly updated by long-term delayed gradients. In this paper, we propose a delay compensated asynchronous Adam (DC-Adam) algorithm to train DNN. In particular, DC-Adam updates the parameters with the moment increment which is the division of the first and the second moments to take the advantage of the original Adam algorithm, and compensates the gradient with the first-order component in its Taylor expansion. Since the delay compensation technique reduces the error of delayed gradients, and the moment increment further counteracts the influence of approximated compensation, DC-Adam converges much more rapidly than ASGD on a computer cluster with moderate computing nodes. We theoretically analyze the Ergodic convergence rate of DC-Adam and compare with DC-ASGD. We implement our DC-Adam algorithm on 61 computing nodes in a computer cluster, and conduct image classification by using LeNet and ResNet, respectively, on the MNIST and CIFAR-10 datasets. The experimental results demonstrate that DC-Adam greatly accelerates the training progress and achieves almost linear speedup rate as increasing the computing nodes.

Modern Graphics Processing Units (GPUs) widely adopt large SRAM based register file (RF) to enable fast context-switch. A large SRAM RF may consume 20% to 40% GPU power, which has become one of the major design challenges for GPUs. Recent studies mitigate the issue through hybrid RF designs that architect a large STT-RAM (Spin Transfer Torque Magnetic memory) RF and a small SRAM buffer. However, the long STT-RAM write latency throttles the data exchange between STT-RAM and SRAM, which deprecates warp scheduler with frequent context switches, e.g., round robin scheduler. In this paper, we propose HC-RF, a warp-scheduler friendly hybrid RF design using novel SRAM/STT-RAM hybrid cell (HC) structure. HC-RF exploits cell level integration to improve the effective bandwidth between STT-RAM and SRAM. By enabling silent data transfer from SRAM to STT-RAM without blocking RF banks, HC-RF supports concurrent context-switching and decouples its dependency on warp scheduler. Our experimental results show that, on average, HC-RF achieves 50% performance improvement and 44% energy consumption reduction over the coarse-grained hybrid design when adopting LRR(Loose Round Robin) warp scheduler.

Relaxed encryption framework which extends hash functions of Merkle-Damg?rd construction to a parallel construction can improve Hash performance by multi-core processor.A proving process was given to show that relaxed encryption framework has no property of collision resistance when processing messages of different size.A new parallel extending algorithm was proposed base on the design of relaxed encryption framework,which remedies the security flaws of the relaxed encryption framework,and the security of the new parallel Hash construction was also discussed.The cryptanalysis shows that the property of collision resistance of the new parallel construction is not weaker than the hash function of Merkle-Damg?rd construction.Experimental results indicate that the new Hash construction performs better when processing messages of large size.

Spin-transfer torque random access memory (STT-RAM) is one of the most promising substitutes for universal main memory and cache due to its excellent scalability, high storage density and low leakage power. A much larger cache capacity in the same die footprint can be implemented with STT-RAM because its area is only 1/9 to 1/3 that of SRAM. However, the non-volatile STT-RAM also has some drawbacks, such as long write latency and high write energy, which limit its application in cache design. To solve the two problems, we relax the retention time of STT-RAM to optimize its write performance and energy, and propose a novel multi-retention STT-RAM hybrid last level cache (LLC) architecture, which is realized with three different kinds of cells. In addition, we design the data migration scheme to manage its block allocation, thus improving overall system performance further. The experiment results show that our multi-retention hybrid LLC reduces the total power consumption by as much as 96.6 % compared with SRAM LLC, while having almost the same (at 99.4 %) instruction per cycle (IPC).

Kernel independent component analysis (KICA) penalizes the correlations among components in a reproducing kernel Hilbert space (RKHS) and performs well in many practical tasks such as speech separation due to its robustness on varying source distributions. Recently, Nyström-KICA (NKICA) incorporates a low-rank approximation and low-complexity sampling method to reduce the computational complexity of KICA. In this paper, we show that the computational complexity of NKICA can be further decreased by implementing the algorithm on the many integrated core (MIC) architecture to meet the requirement of large data processing. Particularly, we parallelize the critical segments with the OpenMP technology and perform the intensive matrix manipulations on a MIC coprocessor. This MIC-based approach has been evaluated on both simulated dataset and the TIMIT dataset. The experimental results confirm the efficiency of our implementation of NKICA on the MIC architecture, and show that it achieves a consistent speedup rate of around 10 on average, and of 12.3 at best, comparing with that performed on single CPU.

The working mechanism of Tunneling Carbon Nanotube Feild Effect transistors (TCNFETs) has been analyzed firstly by defining the sub-threshold plunging voltage and subdividing sub-threshold region into Band-To-Band Tunneling (BTBT) burst region, BTBT sharp region and BTBT smooth region. And then, the effects of device parameters, such as source/drain doping level, oxide thickness, working voltage, on the transfer characteristics are studied with an eye kept on the effect of BTBT burst region. As a conclusion, a reference device parameters choice flow and corresponding criterion are brought out. Research results show that: (1) BTBT burst region make a non-ignorable contribution to the sub-threshold slope. (2) Proper device parameters would contribute to ultra-low sub-threshold slope. (3) BTB tunneling at channel-drain interface would have a negative effect on device performance, which is even could not be suppressed for TCNFETs with small enough energy gap.

TSV in 3DIC introduces a large and fickle parasitic capacitance inevitably, causing serious problems on Power/Signal Integrity (P/SI). In this paper, we give two methods to mitigate TSV-to-TSV coupling, which are buffer insertion and shield insertion. The effect of the buffer insertion and shield insertion are studied by comparison experiment, and the experiment results have proved that these two methods can reduce the coupling capacitance effectively. Factors as location, number and drive capability of buffers in this course are also discussed. TSV-to-TSV coupling reduces by 99 % at maximum. Through combining the two method, we can get a low cost and effective optimization for reduction of TSV-to-TSV coupling in consideration of actual design restrain, which can also be utilized in EDA tools.

The 3D SRAM(three-dimensional static random access memory)will take the place of2D SRAM(two-dimensional static random access memory),and will be widely used in high performance microprocessor.However,3D SRAMstill suffers from the dangers of soft error.A novel3DSRAMsofterroranalysisplatformwasdesignedforstudyingthesofterrorcharacteristicof3DSRAM.Thesofterrorcharacteristicofthe designed 3D SRAMand the original 2D SRAMwere analyzed by using our designed platform.It is found that 3D SRAMand 2D SRAMhave the same upset cross section,but the soft error of3D SRAMis more serious than that of2D SRAM,which makes it difficult to harden 3D SRAMby using error correction codes technologies.At the static test mode,the upset sensitive nodes were only distributed in the memory array of both 3D SRAMand 2D SRAM.It indicates that the logic circuit can’t induce soft error at static test mode.

With the development of maritime information technology and computer technology, wireless communication technology in underwater networks and systems has made great progress and achieved wide range of application, which greatly promoted the development of ocean communication. Due to the presence of severe frequency selective fading, fast fading and slow fading, including all kinds of Noise interference and ISI problem under multipath propagation, especially ISI. In the meantime, in order to improve efficiency in underwater communications, a kind of signal detection algorithm is proposed in the case of interference in this article to deal with this problems-Maximum likelihood detection, this algorithm has a good complexity and relatively a high degree of precision in MIMO-OFDM system. So we do a circuit design based on the ML algorithm. The test result shows that this kind of circuit meets the requirements successfully.

The bubble flow control is an efficient way to achieve deadlock freedom within single dimension network rings.This method has been applied successfully in the supercomputer Bluegene/L.However,it is only suitable for virtual cut-through (VCT)networks.Currently, researchers propose some methods to realize the worm-bubble flow control in networks-on-chip. However,the complicated control logic hampers largely the application of the current worm-bubble flow control strategies.In this paper,one novel design is proposed to realize the efficient and concise worm-bubble flow control.At first,the multi-request input buffer organization (MRIBO)supporting non-atomic buffer allocation is adapted instead of the traditional FIFO buffer organization.Using MRIBO,it is allowed that the flits can be stored in out-order situation between the different packets and each flit can route independently.Based on MRIBO,we design one novel worm-bubble flow control strategy which is suitable for wormhole networks and similar to bubble flow control in VCT networks.We prove that the novel worm-bubble flow control can ensure that those flits can always flow and there is not deadlock in the unidirectional ring when the MRIBO is used.The performance of the novel worm-bubble flow control is analyzed on the BookSim simulator developed at the Standford University,thanks to its modular design,and the availability of a large variety of the classic network implementations.By modifying the source code,new routing algorithms were implemented in the BookSim simulator with little effort.We realize the dimension order routing algorithm (WBFC)and fully adaptive routing algorithm (Adapt-BF)based on the novel worm-bubble flow control.We then compare the average packet latencies of the two algorithms to their counterparts:the traditional dimension order routing algorithm (DOR)and the fully adaptive routing algorithm(Adapt-DL)based on dateline.Torus with different dimensions was used in simulation.To ensure that the comparison is fair,we have assigned the same amount of buffer space to the algorithms under comparison.The results show the performance of novel scheme is superior to the wormhole switching,with nearly 18%reduction in the packets latency for uniform traffic in 8-ary 2-cube Torus.This paper presents a new method to break the atomic demand of packets transmission in wormhole networks and ensure flit route independently by the novel buffer organization structure.In this case,the previous bubble flow control based on local information can be applied into wormhole networks almost without any need for modification.So,this method simplifies the realization of worm-bubble flow control.

In this paper, we proposed two region partition multicast routing algorithms for the 3D mesh Interconnection Network to enhance the overall system performance. The proposed two algorithms shorten the network long path latency. Compared to the based multicast routing algorithm, our simulations with six different synthetic workloads reveal that our architecture acquires high system performance.

Via Geant4 simulations, SEEs are characterized for each die of 3DIC with different heavy ion species and energy in this paper. It is found that the incident ions with high atomic number make the SEE more serious for each die and there are obvious differences on SEE characteristics between each die after the low energy heavy ions striking 3DIC. Our research also indicates that SEE sensitivity of inner dies is no less than that of the outer ones unless the heavy ions stop above the inner dies. It is because the secondary particles induced by nuclear reaction and the scattered heavy ions caused by low energy incident can trigger severe multi-SEEs. It concludes that the inner dies of 3DIC also need to be hardened, and the technologies restraining severe multi-SEEs should be taken for them, if the higher reliability is required.