The minimum bit width of the path metrics at the premise of not affecting the performance are calculated out, in order to reduce the storage resources cost in the design of convolutional code decoders. A simple method is proposed to judge the state nodes which the decoder can reach at each clock cycle during the setup process. Simulation platform to verify the proposed scheme has been set up with the matlab software, after that a decoder of (2,1,8) convolutional code with generating polynomial (561,753) is designed. Result of comparison with other designs shows that the scheme proposed greatly improves the throughput of the decoder at the cost of fewer resources.

The hardware architecture of the DVB-S2 LDPC code encoder and decoder is researched.Decoder with code rate 0.6 and code length 16 200 by using shared memory banks and writing the LLR(Log-Likelihood Ratio) back to the RAM.This structure has low area and high throughput.Simulation result shows the analysis performance of the same code length with different code rate and the same code rate with different code length.When the code length is same,the lower the rate is,the error rate,frame error rate and average number of iteration are lower.The code words of the same code rate but different code length have equal bits proportion of the parity and information bits.But the longer the code length is the stronger the constraint between parity bit and information bit is,the longer the code length is the better the performance is.

A code rate and code length reconfigurable LDPC decoder is proposed which is based on TDMP-NMS algorithm and supports WIMAX standard.The updated node information is used in timely by inserting the shortest extra tine slots.By adopting a filling algorithm based barrel shifter working in an incremental mode,the decoder can support the decoding of four code length LDPC in this standard:576,768,1152,2304.Results show that the decoder designed can fully meet the throughput requirement of WIMAX standard.

The hardware architecture of the DVB-S2 LDPC(Low Density Parity Check Code) code decoder is researched.According to the cyclical feature of the check matrix we have realized a decoder of the DVB-S2 LDPC code whose rate is 3/5 and length is 16 200 bit.Experiment result shows that the total consumption of the LDPC decoder are 24 004 logic cells,6 437 registers and 448 594 bits of RAM.And the throughput of is up to 289 Mbit/s.The structure of decoder using shared memory banks and writing the LLR(Log-Likelihood Ratio) back to the RAM has low area and high throughput.

A logarithmic cyclic shifter based scheme was proposed to improve the operation speed of matrix-vector multiplication in the quasi-cyclic low density parity-check code (QC LDPC) encoding process and then improve the throughput of the encoder. An encoder was designed for an LDPC code defined in the WIMAX standard with a code rate of 1/2 and a code length of 2304. The advantage of resource sharing was fully taken according to the characteristics of the base parity-check matrix which could be converted to a matrix with no two nonnegative elements in the same column in any two adjacent rows by row permutation. Six logarithmic cyclic shifters were used for the parallel calculation of twelve matrix-vector multiplications in the encoding process. Timing simulation and hardware test results show that the proposed solution reduces the resource consumed and improves the throughput effectively compared to other methods.

To overcome the long cycle in digital filter design based on FPGA,a top-down design method based on DSP builder and FPGA is proposed,with which a 4-order cascade IIR filter is designed.With the strong calculation capacity of Matlab,a simulation method in combination of MATLAB with Quartus II is proposed.By converting the complex data to waveform,the simulation result becomes easier for observation,the simulation function of Quartus II is also enhanced.The results show that the IIR digital filter can fully meet the design requirement.

To effectively reduce the hardware cost of partial parallel QC-LDPC decoder, a new architecture is proposed. Based on a simplified TDMP algorithm with min sum algorithm, not only does it have a low complexity, but it can also achieve a fast convergence speed. By adopting a new shuffle network which is similar to Benes network working in an incremental mode, implementation of the interconnection network between memory units and processing units can be greatly simplified. Fixed point simulation is done in compare with float point. According to the results, an optimal quantization scheme for all kinds of data in the decoding process is proposed. The proposed architecture has certain practical value

To overcome the defects of current convolutional code decoders in occupying too much resource and being with low working frequency,a new decoder of(2,1,8) convolutional code based on Viterbi algorithm is designed.To effectively improve the operating frequency of the decoder,registers are used to store the path metrics and survivor path of each state.By analyzing the relationship among one state and its former states which come to it,a simple way to realize the process in hardware is found.The minimum register width for storing the path metric of each state is calculated by analyzing the change rule of the path metric difference between any two states.The source code is written and then compiled,synthesized and simulated on the Quartus2 integrated development platform.The experimental results show that the decoder not only has a higher working frequency and shorter output delay,but also consumes less resource,and thus is of certain practical value.