With rapid advancements in information technology, the security of hard drives has garnered widespread attention from both enterprises and individuals, making it a highly critical topic of research. At present, data encryption for storage security purposes is often managed using application software, hard drive controllers, or bridge encryption chips. The recommended encryption algorithm is the Advanced Encryption Standard (AES), as defined by the National Institute of Standards and Technology (NIST). Software-based encryption can increase system overhead and is vulnerable to memory attacks, such as cold boot or timing attacks. Because the computational resources of hard drive controllers are limited, their security capabilities are also limited. Although controller chips can provide encryption, their utilization is still hindered by risks such as theft-related data leaks. Encryption bridge chips are more secure and efficient. Research efforts thus far have focused on improving the speed of cryptographic algorithms, often neglecting integration with communication protocols. In this paper, we propose a Serial Advanced Technology Attachment (SATA) encryption bridge module design with automatic activation of AES-XTS functionality by analyzing the characteristics of the SATA protocol, with the results showing that the encryption loss for sequential read–write is under 10

Data prefetching is an essential technique that bridges the memory wall by speculatively loading data to hide memory access latency. Although Reinforcement Learning (RL)-based prefetchers such as Pythia show significant potential, they remain limited by state representations, high hardware overhead, and the inability to dynamically coordinate the prefetch degree and direction. To address these limitations, we propose 3D-DP, a novel prefetcher based on Deep Reinforcement Learning (DRL). 3D-DP replaces large Q-tables with a lightweight fully connected neural network. This approach allows for the direct processing of high-dimensional state features, alleviating the state aliasing issues introduced by hash-based indexing. It also addresses slow-start issues thanks to the network’s ability to generalize across parameters. 3D-DP also introduces an adaptive control mechanism that dynamically determines the optimal prefetch degree for each memory page based on its access history and current system load. This is complemented by a low-overhead algorithm for predicting prefetch direction, enabling fine-grained coordination of both the amount and direction of prefetched data. For practical hardware implementation, we also propose 3D-DP-TQ, a quantized version of 3D-DP that leverages ternary quantization to compress the storage overhead to just 4.92 KB. Our evaluations using the SPEC CPU 2006 and 2017 benchmarks show that 3D-DP outperforms state-of-the-art prefetchers, achieving performance improvements of 10.2

In the astronomical observation field, determining the allocation of observation resources of the telescope array and planning follow-up observations for targets of opportunity (ToOs) are indispensable components of astronomical scientific discovery. This problem is computationally challenging, given the online observation setting and the abundance of time-varying factors that can affect whether an observation can be conducted. This paper presents ROARS, a reinforcement learning approach for online astronomical resource-constrained scheduling. To capture the structure of the astronomical observation scheduling, we depict every schedule using a directed acyclic graph (DAG), illustrating the dependency of timing between different observation tasks within the schedule. Deep reinforcement learning is used to learn a policy that can improve the feasible solution by iteratively local rewriting until convergence. It can solve the challenge of obtaining a complete solution directly from scratch in astronomical observation scenarios, due to the high computational complexity resulting from numerous spatial and temporal constraints. A simulation environment is developed based on real-world scenarios for experiments, to evaluate the effectiveness of our proposed scheduling approach. The experimental results show that ROARS surpasses 5 popular heuristics, adapts to various observation scenarios and learns effective strategies with hindsight.

Certain transients require regular observations over several days at intervals of hours or shorter,which cannot be accomplished by telescopes at a single site.The deployment of globally distributed telescopes at geographic locations of different longitudes enables the periodic monitoring of transients through relay observation.However,the simultaneous relay observation of numerous targets requires a telescope array of multiple telescopes that can be efficiently coordinated,and an automated scheduler for the array.This paper proposes IPROS,an integer programming model relay observation scheduler for a telescope array,that accounts for the entire process of relay observation and is consistent with the practical scenarios.We introduce the integer programming mathematical model for the relay observation scheduling problem with the telescope array,upon which the scheduler is based.Additionally,we propose an algorithm to provide a comprehensive formulation of the optimization objective of minimizing cadence deviation in the model.Experimental results demonstrate that the relay observation scheduler based on the integer programming model can effectively address the telescope array relay observation problem.It shows superiority over a scheduler with non-specific consideration of relay observation in the modeling and a scheduler based on greedy thought.

The branch predictor is widely used to enhance processor performance, but it also constitutes one of the major energy-consuming components in processors. We found that approximately 32% of instruction blocks in a decoupled frontend do not contain branch instructions, while 30.8% of instruction blocks contain only conditional branches. However, because the type of instructions within a block cannot be determined during prediction, branch prediction must be executed every cycle. In this work, we propose the next block type (NBT) and no branch sequence table (NST) for predicting instruction block types. These mechanisms occupy minimal space and are straightforward to implement. For a four-way out-of-order processor, the NBT and NST reduce the branch predictor’s energy consumption by 52.36% and processor’s energy consumption by 4.1% without sacrificing the processor’s instructions per cycle (IPC) and branch prediction accuracy.

Modern GPUs employ a multi-level cache hierarchy where several requests missing in L1 Caches can be redirected to L2 Cache simultaneously. Therefore, the memory space of L2 Cache is divided into multiple partitions. A partition corresponding to a DRAM channel is composed of two subpartitions, each of which featuring a L2 Cache bank with a 32-byte/cycle data port. Given that the NoC datapath between L2 and L1 Caches also has a 32-byte bandwidth. Therefore, a request associating 128-byte data that are obtained from the L2 cache-line requires four cycles for completion, leading to bandwidth fragmentation and low resource utilization when request distribution is uneven. To address this issue, we propose the BASH architecture, which aggregates four subpartition data ports into a logical 128-byte channel and incorporates intra-group round-robin scheduling. This enables full processing of a request data transmission within a single cycle for a subpartition. Without modifying the existing model, our solution significantly improves L2 bandwidth utilization and system performance. Experimental results demonstrate that BASH can increase data port utilization by 15.7% compared to the baseline GPU, with an average performance improvement of 23.1%.

The distributed telescope array offers promise for conducting large-sky-area, high-frequency time-domain surveys. Multiple telescopes can be deployed at each observation site, so intrasite observation task scheduling is crucial for enhancing observation efficiency and quality. Efficient use of observable time and rapid response to special situations are critical to maximize scientific discovery in time-domain surveys. Besides, the competing scientific priorities, time-varying observation conditions, and capabilities of observation equipment, lead to a vast search space of the scheduling. So with the increasing number of telescopes and observation fields, balancing computational time with solution quality in observation scheduling poses a significant challenge. Informed by the seminal contributions of earlier studies on a multilevel scheduling model and global scheduler for a time-domain telescope array, this study is devoted to further exploring the site scheduler. Formulating the observation scheduling of multiple telescopes at the site as a cooperative decision-making problem, this paper proposes GRRIS, a real-time intrasite observation scheduling scheme for the telescope array using graph and reinforcement learning (RL). It employs a graph neural network to learn node features that can embed the spatial structure of the observation scheduling. An algorithm based on multi-agent RL is designed to efficiently learn the optimum allocation policy of telescope agents to field nodes. Through numerical simulations with real-world scenarios, GRRIS can achieve up to a 22% solution improvement over the most competitive scheme. It offers better scalability and subsecond decision speed, meeting the needs of observation scheduling control for future distributed telescope arrays.

GPUs are comprised of numerous streaming multiprocessors (SMs) tailored for high performance computing. SMs incorporate private L1 caches to facilitate swift data access for thousands of threads running concurrently inside SMs. Requests that miss in L1 caches are directed to L2 caches that are shared by all SMs to retrieve the desired data, which takes much longer time compared with the delay of accessing L1 cache. Due to the locality among tasks running on SMs, the same data block might be accessed by requests from various SMs, leading to data replication across multiple L1 caches. Notably, data replication is prevalent in applications exhibiting high data locality. In order to capitalize on the data replications among L1 caches, we propose routing requests destined for L2 cache to other L1 caches that are predicted to contain the desired data, extending the access scope of requests. Consequently, we introduce a Pseudo-Cache positioned adjacent to the network on chip on L2 cache side, offering a global perspective of all SMs to manage these predictions effectively. Moreover, we implement the data path for request forwarding in a cost-effective manner, leveraging the existing network structure. Experimental results underscore the efficacy of our approach, showcasing an average 16.3% performance enhancement for applications characterized by substantial data replication on GPUs.

Recurrent neural networks (RNNs) have produced significant results in many fields, such as natural language processing and speech recognition. Owing to their computational complexity and sequence dependencies, RNNs need to be deployed on customized hardware accelerators to satisfy performance and energy-efficiency constraints. However, designing hardware accelerators for RNNs is challenged by the vast design space and the reliance on ineffective optimization. An efficient automated design space exploration (DSE) strategy that can balance conflicting objectives is wanted. To address the low efficiency and insufficient universality of the resource allocation process employed for hardware accelerators, we propose an automated two-stage design space exploration (DSE) strategy for customized RNN accelerators. The strategy combines a genetic algorithm (GA) and a reinforcement learning (RL) algorithm, and it utilizes symmetrical exploration and exploitation to find the optimal solutions. In the first stage, the area of the hardware accelerator is taken as the optimization objective, and the GA is used for partial exploration purposes to narrow the design space while maintaining diversity. Then, the latency and power of the hardware accelerator are taken as the optimization objectives, and the RL algorithm is used in the second stage to find the corresponding Pareto solutions. To verify the effectiveness of the developed strategy, it is compared with other algorithms. We use three different network models as benchmarks: a vanilla RNN, LSTM, and a GRU. The results demonstrate that the strategy proposed in this paper can provide better solutions and can achieve latency, power, and area reductions of 9.35%, 5.34%, and 11.95%, respectively. The HV of GRMD is reduced by averages of 6.33%, 6.32%, and 0.67%, and the runtime is reduced by averages of 18.11%, 14.94%, and 10.28%, respectively. Additionally, given different weights, it can make reasonable trade-offs between multiple objectives.

Location-based cross-matching is a preprocessing step in astronomy that aims to identify records belonging to the same celestial body based on the angular distance formula. The traditional approach involves comparing each record in one catalog with every record in the other catalog, resulting in a one-to-one comparison with high computational complexity. To reduce the computational time, index partitioning methods are used to divide the sky into regions and perform local cross-matching. In addition, cross-matching algorithms have been adopted on high-performance architectures to improve their efficiency. But the index partitioning methods and computation architectures only increase the degree of parallelism, and cannot decrease the complexity of pairwise-based cross-matching algorithm itself. A better algorithm is needed to further improve the performance of cross-matching algorithm. In this paper, we propose a 3d-tree-based cross-matching algorithm that converts the angular distance formula into an equivalent 3d Euclidean distance and uses 3d-tree method to reduce the overall computational complexity and to avoid boundary issues. Furthermore, we demonstrate the superiority of the 3d-tree approach over the 2d-tree method and implement it using a multi-threading technique during both the construction and querying phases. We have experimentally evaluated the proposed 3d-tree cross-matching algorithm using publicly available catalog data. The results show that our algorithm applied on two 32-core CPUs achieves equivalent performance than previous experiments conducted on a six-node CPU-GPU cluster.

The analysis of temporal evolution patterns and interactions in complex, time-varying flow field numerical simulations is crucial to understanding the underlying mechanisms. In order to effectively describe the evolution of the flow field, feature extraction can effectively identify high-level feature regions in the flow field, and feature tracking can match relationships in the time dimension of the flow field, thus recognizing the generation of feature events. In this paper, a feature point classifier based on local extraction methods was designed to binary-judge flow field data points, and a feature region diffusion algorithm was used to extract feature regions. Based on the feature extraction results, this paper proposes a new feature similarity measurement method based on spatial distribution optimization, and implements a globally optimized feature tracking method based on Directed Acyclic Graph (DAG) graphs based on this measurement method. This method effectively solves the problem of tracking interruptions and tracking errors caused by using volume overlap as a measurement standard in traditional tracking methods, and eliminates the need for setting thresholds in traditional methods. Finally, the effectiveness of the feature extraction and feature tracking methods is proven through several experimental data.

针对目前计算机组成与体系结构课程中教学内容缺少产出导向和知识贯穿、实验教学综合性不强、评价手段单一 3个问题,提出基于项目制的课程改革和探索,围绕"奋斗一学期,造台计算机"这一复杂工程问题,从重塑以产出为牵引的知识体系,设计项目式实践教学体系,打造"理论+实践"混合式授课模式,建立多元化、分层次、过程性的评价这4方面阐述改革措施,并说明改革成效.

针对国内高校计算机专业数字逻辑与数字系统课程无法满足信息领域人才培养需求的问题,以系统能力培养为目标,以虚实结合的实验平台为载体,围绕单周期32位MIPS(每秒处理百万级的机器语言指令数)处理器设计的主线任务,提出了"点—线—面"三层递进式实践教学体系,从课后练习、实验教学和综合实践3个维度形成对课程核心知识点的纵向贯穿.通过该实践教学改革,使学生在计算机系统能力上得到充分的训练,为后续课程开发更加复杂的流水线处理器和片上系统奠定了坚实的知识和能力基础.

The on-chip memories of GPUs, including the register file, shared memory and L1 cache, can provide high bandwidth and low latency access for the temporary storage of data. The capacity of L1 cache can be increased by using the registers/shared memory that are unassigned to any warps/thread blocks or released after warps/thread blocks are finished as cache-lines. In this paper, we propose two techniques to manage requests for on-chip memories to improve the efficiency of L1 cache on the base of leveraging registers and shared memory as cache-lines. Specifically, we develop a data transferring policy which is triggered when cache-lines are recalled by the first register or shared memory accesses of warps that are newly launched to prevent the data locality from being destroyed. Additionally, we design a parallel issue scheme by exploring the parallel feature of requests of an instruction accessing the register file, shared memory and L1 cache to decrease the processing latency and hence increase the throughput of instructions. The experimental results demonstrate that our approach improves the performance by 15% over prior work.

人工智能的迅速发展使得现代卷积神经网络在图像识别和分类任务上取得了巨大成功.然而,复杂神经网络模型不断向更深层的网络结构发展,在面积、功耗受限的移动设备上部署时无法保持高性能和高精度.针对该问题,面向可编程阵列芯片(FPGA)平台提出了一种基于软硬件协同方法的MobileNet-SSD目标检测硬件加速器设计.首先采用剪枝和量化算法对原始MobileNet-SSD模型进行压缩,其中剪枝是针对点卷积层参数冗余问题而提出的卷积核剪枝算法,量化则是将训练后的网络模型中的浮点数统一转换为定点数参与卷积计算.然后,设计了一种可配置的卷积计算加速阵列,通过循环分块实现不同规模网络层的多粒度并行.在此基础上,进一步设计了一种针对输入缓存的行缓存优化机制,结合直接存取存储器(DMA)和数据流接口传输数据解决传输延迟的瓶颈.实验表明,所提出的目标检测系统的性能功耗比相较于CPU和GPU分别提升了 79倍和1.9倍,相比于以往工作中提出的目标检测系统具有更高的准确度和更优的性能.

GPUs provide megabytes of registers and shared memories to maintain the contexts for thousands of threads and enable fast data sharing amongst threads of a thread block, respectively. Besides, GPUs employ L1 cache to provide the high bandwidth service for memory requests. However, the average L1 cache capacity per thread is very limited, resulting in cache thrashing which in turn impairs the performance. Meanwhile, many registers and shared memories are unassigned to any warps or thread blocks. Moreover, registers and shared memories that are assigned can be idle when warps or thread blocks are finished. Exploiting the above insights, we propose Virtual-Cache to cost-effectively increase the effective size of L1 cache by utilizing the unassigned and released registers and shared memories as cache-lines in this paper. Specifically, we leverage the unassigned registers and shared memories to serve cache requests directly. Regarding the registers assigned to a warp, they can work as cache-lines after the warp completes the execution and before they are accessed again by a new launched warp. Regarding the shared memories of a thread block, they are enabled to serve cache requests when the thread block is finished till they are referenced by shared memory instructions of the relaunched thread block. The register file, shared memory and L1 cache are physically independent but logically unified as a large virtual cache with redesigned cache-line management. We develop the control and data path for the register file, making the register file accessible for cache requests by borrowing an operand collector to serve the cache requests. We also expand the control and data path for the shared memory to serve the cache requests. Our evaluation results show that Virtual-Cache makes the performance improved by 28% over the previously proposed cache management technique for cache-sensitive applications.

Graphics processing units (GPUs) employ the single instruction multiple data (SIMD) hardware to run threads in parallel and allow each thread to maintain an arbitrary control flow. Threads running concurrently within a warp may jump to different paths after conditional branches. Such divergent control flow makes some lanes idle and hence reduces the SIMD utilization of GPUs. To alleviate the waste of SIMD lanes, threads from multiple warps can be collected together to improve the SIMD lane utilization by compacting threads into idle lanes. However, this mechanism induces extra barrier synchronizations since warps have to be stalled to wait for other warps for compactions, resulting in that no warps are scheduled in some cases. In this paper, we propose an approach to reduce the overhead of barrier synchronizations induced by compactions. In our approach, a compaction is bypassed by warps whose threads all jump to the same path after branches. Moreover, warps waiting for a compaction can also bypass this compaction when no warps are ready for issuing. In addition, a compaction is canceled if idle lanes can not be reduced via this compaction. The experimental results demonstrate that our approach provides an average improvement of 21% over the baseline GPU for applications with massive divergent branches, while recovering the performance loss induced by compactions by 13% on average for applications with many non-divergent control flows.

In this paper, we propose a real-time hardware naive Bayes classifier (NBC) which is implemented on field programmable gate array (FPGA). We first use logarithm transformation based look-up table and float-to-fixed point process to simplify the calculations in naive Bayes classification algorithm. The methods clear up the multiplication and division operations of floating points completely. Based the simplified algorithm, we design our hardware architecture which includes both training and inference part. A novel format of logarithm look-up table with very limited items and a shifter in it are working together to calculate the logarithm value of any number. There are several processing element (PE) arrays in the accelerator where each PE in an array is running in parallel, which speed up the classification process remarkably. The experiments prove that the proposed accelerator has much better real-time efficiency than the general processor, some hardware Bayes classifiers and convolutional neural network (CNN) accelerators. It outperforms the NBC and semi-NBC accelerators and costs far less resources on chip than many CNN accelerators. Its utilization of LUT, FF and BRAM is only 10%, 0.05% and 2% of CNN accelerators on average. The experimental results over five datasets of different magnitudes show the accelerator has almost no loss of classification accuracy comparing with ARM Cortex-A9 processor. Their deviation of the classification accuracy is only 0.39% on average. What's more, it improves the performance of the training phase and the inference phase about 7.9+e4 and 8.3+e4 on average, respectively.

With the popularity of GPU which has the high performance computing feature, more and more algorithms have been successfully transplanted to the GPU platform and achieved high efficiency. But existing videos or images processing methods, such as demosaicing algorithm, have not fully exploited the parallel computing capacity of heterogeneous processing platform and the video frame rates can’t meet real-time requirements. In order to take full advantage of the computing power of GPU under the heterogeneous processing platform, an optimization scheme is proposed in this paper. We use the demosiacing algorithm as a case and modify the algorithm. By exploiting the GPU’s memory hierarchy, the optimization scheme improves the parallelism of the algorithm while reducing the memory access latency, and greatly reduces the execution time. Then we achieve the zero-copy at the same time. The experimental results show that optimization version has a significant performance improvement, the optimized OpenCL version is up to 6x comparing with the basic OpenCL version about kernel execution.