Data Processing Units (DPUs) have been deployed in disaggregated storage systems to accelerate data transmission. However, in this paper, we observe that during data access in disaggregated storage, the address translation process incurs significant CPU computation overhead and leads to high system latency. Additionally, in large-scale storage systems, the address indexing structures also consume substantial memory space, incurring high costs. To address these challenges, we propose HiDPU, a DPU-oriented hybrid indexing scheme optimized for disaggregated storage systems. Our solution introduces a multi-level indexing structure to alleviate the limitations of DPU memory resources, constrained computational power, and the high DPU-host interaction overhead. Mapping entries for the storage space are divided into different kinds of segments (i.e., accurate, PTHash, and LPTHash) to leverage address continuity. A layered learned index is constructed across these segments to enhance memory efficiency. To further reduce DPU-host interactions, small upper-layer indexes and frequently accessed metadata are maintained on the DPU, limiting interactions to a single instance. HiDPU also implements a two-phase asynchronous index update strategy to ensure index consistency between the DPU and host memory, while minimizing performance overhead. Experimental results on Huawei's Hi1823 DPU demonstrate that HiDPU achieves up to 92% memory savings and improves query performance by up to 6.3x compared to existing solutions.

The rapidly growing mobile market is pushing flash storage manufacturers to expand capacity into the terabyte range. However, this presents a significant challenge for mobile storage management: more logical-to-physical page mappings are desired to be efficiently managed and cached while the available caching space is extremely limited. This motivates us to shift toward a new learning-based paradigm: rather than maintaining mappings for individual pages, the learning-based approach can represent mapping relationships for a set of continuous pages. However, to construct linear models, existing methods that either consume the already-limited memory space or reuse flash garbage collection demonstrate poor model construction capabilities or significantly degrade flash performance, making them impractical for real-world use. In this paper, we propose LFTL, a practical, learning-based on-demand flash translation layer design for flash management in mobile devices. In contrast to prior work that centered around gathering sufficient mappings for linear model construction, our key insight is that linear patterns can be extracted and refined by leveraging the orderly, LPA-aligned write stream typical of mobile devices. By doing this, highly accurate linear models can be constructed regardless of the constraints of mobile device's cache limitation. We have implemented a fully functional prototype of LFTL based on FEMU. Our evaluation results show that LFTL is more adaptable to memory-constrained storage devices than state-of-the-art learning-based approaches.

F2FS, a log-structured filesystem, has gained widespread adoption in Android systems. However, F2FS relies on coarse-grained checkpointing for crash recovery. When triggered, this mechanism significantly degrades system performance by blocking file writes. Additionally, F2FS's checkpointing approach may not fully recover file data and metadata to a consistent state after a crash. Given these limitations, it is crucial to design a new journaling mechanism for F2FS that provides fine-grained crash recovery. While journaling methods are well-studied for in-place-update filesystems (such as JBD2 for EXT4), directly applying these state-of-the-art techniques to F2FS - an out-of-place-update filesystem - does not yield similar benefits. In this paper, we propose a novel journaling technique, called F2FSJ, for F2FS with ordered journal mode. Catering to the out-of-place update features of F2FS, F2FSJ incorporate several innovative designs. First, in F2FSJ, only metadata changes are journaled and committed after data flushing, by which I/O and storage overheads can be mitigated. Second, we propose a decentralized journal design by embedding journal logs into inodes, which significantly reduces lock contention and interference when recording metadata changes. Third, we propose an epoch-based approach with a novel data/controlplane decoupling mechanism, which eliminates waiting times during journal period transfers. Finally, for journal apply, we propose a fast-forward-to-latest approach to consolidate multiple small updates into one update for reducing small writes. We have implemented a fully functional prototype of F2FSJ and conducted extensive experiments. Our experimental results demonstrate that F2FSJ can effectively reduce the checkpointing time by up to 4.9x and reduce the latency by up to 35% compared with F2FS. F2FSJ is open-sourced for public access.

Traditional DRAM-based memory solutions face challenges, including high energy consumption and limited scalability. Non-Volatile Memory (NVM) offers low energy consumption and high scalability. However, security challenges, particularly data remanence vulnerabilities, persist. Prevalent methods such as the Bonsai Merkle Tree (BMT) are employed to ensure data security. However, the consistency requirements for integrity tree updates have led to performance issues. It is observed that compared to a secure NVM system without persistent secure metadata, the average overhead for updating and persisting the BMT root with persistent secure metadata is as high as 2.48 times. Therefore, this paper aims to mitigate these inefficiencies by leveraging the principle of memory access locality. We propose the Dynamic Construction and Adjustment of Skewed Bonsai Merkle Tree (DCAS-BMT). The DCAS-BMT is dynamically built and continuously adjusted at runtime according to access weights, ensuring frequently accessed memory blocks reside on shorter paths to the root node. This reduces the verification steps for frequently accessed memory blocks, thereby lowering the overall cost of memory authentication and updates. Experimental results using the USIMM memory simulator demonstrate that compared to the widely used BMT approach, the DCAS-BMT scheme shows a performance improvement of 34.1%.

Nowadays, data centers consolidate latency-critical (LC) tenants and best-effort (BE) tenants on the same cloud platform to increase resource utilization and reduce costs. In such a scenario, the underlying distributed storage systems are responsible for guaranteeing SLOs for LC tenants while maximizing bandwidth for BE tenants. As high-performance NVMe SSDs are widely deployed, how to make full use of their performance capabilities and guarantee SLOs has become an urgent problem. However, current methods restrict the performance capabilities of NVMe SSDs based on a conservative offline model, and also ignore runtime changes in tenant loads and device states, which definitely affect the performance capabilities. In this paper, we present zQoS, an efficient technique that unleashes full performance capabilities of NVMe SSDs, and increases bandwidth of BE tenants while guaranteeing SLOs of LC tenants. First, zQoS builds a more accurate offline performance model for NVMe SSDs to accurately reflect their performance characteristics. Second, a fine-grained online adjustment mechanism is proposed to dynamically adjust the performance capabilities of NVMe SSDs at runtime. Finally, to cope with abrupt load changes, an adaptive per-tenant adjustment method is designed to guarantee SLOs and increase utilization. We evaluate zQoS in a wide variety of mixed workload scenarios. Results show that zQoS significantly outperforms the state-of-the-art approaches. It achieves up to a 17x increase in BE tenant bandwidth without violating LC tenant SLOs.

Multi-scale detection based on Feature Pyramid Networks (FPN) has been a popular approach in object detection to improve accuracy. However, using multi-layer features in the decoder of FPN methods entails performing many convolution operations on high-resolution feature maps, which consumes significant computational resources. In this paper, we propose a novel perspective for FPN in which we directly use fused single-layer features for regression and classification. Our proposed model, You Only Look One Hourglass (YOLOH), fuses multiple feature maps into one feature map in the encoder. We then use dense connections and dilated residual blocks to expand the receptive field of the fused feature map. This output not only contains information from all the feature maps, but also has a multi-scale receptive field for detection. The experimental results on the COCO dataset demonstrate that YOLOH achieves higher accuracy and better run-time performance than established detector baselines, for instance, it achieves an average precision (AP) of 50.2 on a standard 3× training schedule and achieves 40.3 AP at a speed of 32 FPS on the ResNet-50 model. We anticipate that YOLOH can serve as a reference for researchers to design real-time detection in future studies. Our code is available at https://github.com/wsb853529465/YOLOH-main.

Recently,solid-state drives(SSDs)have been used in a wide range of emerging data processing systems.Essentially,an SSD is a complex embedded system that involves both hardware and software design.For the latter,firmware modules such as the flash translation layer(FTL)orchestrate internal operations and flash management,and are crucial to the overall input/output performance of an SSD.Despite the rapid development of new SSD features in the market,the research of flash firmware has been mostly based on simulations due to the lack of a realistic and extensible SSD development platform.In this paper,we propose SoftSSD,a software-oriented SSD development platform for rapid flash firmware prototyping.The core of SoftSSD is a novel framework with an event-driven programming model.With the programming model,new FTL algorithms can be implemented and integrated into a full-featured flash firmware in a straightforward way.The resulting flash firmware can be deployed and evaluated on a hardware development board,which can be connected to a host system via peripheral component interconnect express and serve as a normal non-volatile memory express SSD.Different from existing hardware-oriented development platforms,SoftSSD implements the majority of SSD components(e.g.,host interface controller)in software,so that data flows and internal states that were once confined in the hardware can now be examined with a software debugger,providing the observability and extensibility that are critical to the rapid prototyping and research of flash firmware.We describe the programming model and hardware design of SoftSSD.We also perform experiments with real application workloads on a prototype board to demonstrate the performance and usefulness of SoftSSD,and release the open-source code of SoftSSD for public access.

针对目前计算机组成与体系结构课程中教学内容缺少产出导向和知识贯穿、实验教学综合性不强、评价手段单一 3个问题,提出基于项目制的课程改革和探索,围绕"奋斗一学期,造台计算机"这一复杂工程问题,从重塑以产出为牵引的知识体系,设计项目式实践教学体系,打造"理论+实践"混合式授课模式,建立多元化、分层次、过程性的评价这4方面阐述改革措施,并说明改革成效.

Object detection algorithms can benefit from multi-level features, which encompass both high-level semantic information and low-level location details. However, existing detection methods face numerous challenges in effectively utilizing these multi-level features. Most existing detection techniques utilize simplistic operations such as feature addition or concatenation to fuse multi-level features, thereby failing to effectively suppress redundant information. Consequently, the performance of these algorithms is significantly constrained in complex scenarios. To address these limitations, this paper presents a novel feature extraction network that incorporates joint modeling and multi-dimensional feature fusion. Specifically, the network partitions the features of each level into tiles and employs hybrid self-attention mechanisms to extract these grouped features more comprehensively. Additionally, a hybrid cross-attention-based approach is utilized to regulate the transmission proportion of each grouped feature, facilitating the seamless integration of high-level semantic features obtained from deep encoders and the low-level position details retained by the pipeline. Consequently, the network effectively suppresses noise and enhances performance. Experimental evaluation on the MS COCO dataset demonstrates the effectiveness of the proposed approach, achieving an impressive accuracy of 54.3

The lifetime of NAND flash cells significantly degrades with feature-size reductions and multilevel cell technology. On the other hand, we have more and more approximate data, such as images and videos that are more error tolerant than regular data like text. In this article, we propose Rebirth-FTL, which reuses faulty blocks that contain uncorrectable errors to store approximate data for lifetime optimization. Rebirth-FTL effectively manages two spaces, namely, the approximate space and the normal space, with an efficient address translator, a coordinated garbage collection, and a differential wear leveler. In addition, we develop an migration times restriction (MTR) policy to restrict the movement of the approximate data in the approximate space. We also develop a scheme to pass approximate information from userland to kernel space in Linux. Finally, a lifetime model is presented for lifetime analysis. Our experimental results show that Rebirth-FTL can extend the lifetime by 41.63% on average.

Recently, solid-state drives (SSDs) have been used in a wide range of emerging data processing systems. Essentially, an SSD is a complex embedded system that involves both hardware and software design. For the latter, firmware modules such as the flash translation layer (FTL) orchestrate internal operations and flash management, and are crucial to the overall I/O performance of an SSD. Despite the rapid development of new features of SSDs in the market, the research of flash firmware has been mostly simulation-based due to the lack of a realistic and extensible SSD development platform. In this paper, we propose SoftSSD, a software-defined SSD development platform for rapid flash firmware prototyping. The core of SoftSSD is a novel framework with an event-driven programming model. With the programming model, new FTL algorithms can be implemented and integrated into a full-featured flash firmware in a straightforward way. The resulting flash firmware can be deployed and evaluated on a hardware development board, which can be connected to a host system via PCIe and serve as a normal NVMe SSD. Different from existing hardware-oriented development platforms, SoftSSD implements the majority of SSD components (e.g., host interface controller) in software so that data flows and internal states that were once confined in the hardware can now be examined with a software debugger, providing the observability and the extensibility that are critical to the rapid prototyping and research of flash firmware. This paper describes the programming model and hardware design of SoftSSD. We also perform experiments with real application workloads on a prototype board to demonstrate the performance and usefulness of SoftSSD and released the open-source code of SoftSSD for public access.

Although the GPS-based positioning is ubiquitous for its high precision, the high power consumption brought by the high sampling frequency and the poor GPS signal penetration limits its availability in locating low-power mobile devices (especially mobile phones). As a promising complement, the cellular-based positioning has attracted great attention since it consumes much less power as well as its higher availability. However, the sparsity of cellular-based data (due to lower sampling rate) and large localization errors make the measurement accuracy becomes the main challenge of the cellular-based positioning. hidden Markov model can well solve the problem of positioning error of GPS data, but it is less accurate when applied to map matching of cellular-base data. Therefore, to improve accuracy, in this article, we propose a novel algorithm called the tailored hidden Markov model (THMM) that is optimized for the cellular-based data. Specifically, the geometric, the topological, and the probabilistic characteristics have been considered and fully exploited in the THMM design. Our proposed schemes are evaluated using real-world motor vehicle movement trajectories collected in Tianjin and the experimental results are encouraging compared with the state-of-the-art algorithms.

大数据应用对内存容量的需求越来越大,而在大数据应用中,以动态随机存储器为内存介质的传统存储器所凸显出来的问题也越来越严重.计算机设计者们开始考虑用非易失性内存去替代传统的动态随机存储器内存.非易失性内存作为非易失的存储介质,不需要动态刷新,因此不会引起大量的能量消耗;此外,非易失性内存的读性能与动态随机存储器相近,且非易失性内存单个存储单元的容量具有较强的可扩展性.但将非易失性内存作为内存集成到现有的计算机系统中,需要解决其安全性问题.传统的动态随机存储器作为内存介质掉电后数据会自动丢失,即数据不会在存储介质中驻留较长时间,而当非易失性内存作为非易失性存储介质时,数据可以保留相对较久的时间.若攻击者获得了非易失性内存存储器的访问权,扫描存储内容,便可以获取内存中的数据,这一安全性问题被定义为数据的"恢复漏洞".因此,在基于非易失性内存模组的数据中心环境中,如何充分有效地利用非易失性内存,并保证其安全性,成为迫切需要解决的问题.该文从非易失性内存的安全层面出发,对近年来的研究热点及进展进行介绍.首先,该文总结了非易失性内存所面临的主要安全问题,如数据窃取、完整性破坏、数据一致性与崩溃恢复,以及由加解密和完整性保护技术引入而导致的系统性能下降等问题.然后,针对上述各问题,对组合计数器模式加密技术、完整性保护技术扩展的默克尔树、数据一致性与崩溃恢复技术,以及相关优化方案作了详细介绍.最后,对全文进行了总结,并对非易失性内存未来需要进一步关注的问题进行了展望.

Deep convolutional neural networks (DCNNs) are one of the most promising models for pattern recognition and classification tasks . With the development of wearable devices and the Internet of Things (IoTs), integrating DCNNs onto embedded and portable devices is becoming more and more desirable. However, it is hard to deploy large-scale DCNNs that consume huge power and need many hardware resources in embedded devices with limited power and resources. Previous studies propose that stochastic computing (SC) can replace the resource-consuming binary arithmetic operation in DCNN, which not only simplifies the hardware implementation of arithmetic units but also has the potential to meet the low power requirements of embedded devices. However, bit-streams in SC usually have more bits than the original binary numbers, which inevitably leads to greater storage pressure. To overcome these limitations, in this work, we use Multi-Level Cell (MLC) Phase Change Memory (PCM) which has very low leakage power and high density to replace dynamic random access memory (DRAM) as the weight storage of DCNN. We design SC-PCM, an MLC PCM optimization technology dedicated to SC, which optimizes the write latency and power consumption of MLC PCM. We propose an effective layer-wise multi-precision SC-DCNN model, which reduces the scale of the neural network without sacrificing the accuracy of the DCNNs.

The significant increase in the computation and parameter storage costs of CNNs promotes its development in various applications and restricts its deployment in edge devices as well. Therefore, many neural network pruning methods has been proposed for neural network compression and acceleration. However, there are two major limitations to these methods: First, prevailing methods usually design single pruning criteria for the primitive network and fail to consider the diversity of potential optimal sub-network structure. Second, these methods utilize traditional training method to train the sub-network, which is not enough to develop the expression ability of the sub-network under the current task. In this paper, we propose Model Selection - Knowledge Distillation (MS-KD) framework to solve the above problems. Specifically, we develop multiple pruning criteria for the primitive network, and the potential optimal structure is obtained through model selection. Furthermore, instead of traditional training methods, we use knowledge distillation to train the learned sub-network and make full use of the structure advantages of the sub-network.To validate our approach, we conduct extensive experiments on prevalent image classification datasets. The results demonstrate that our MS-KD framework outperforms the existing methods under a wide range of data sets, models, and inference costs.

Shingled Magnetic Recording (SMR) Disks are adopted as a high-density, non-volatile media that significantly precedes conventional disks in both the storage capacity and cost. However, inefficient read-modify-writes (RMWs) greatly challenge the management of SMR disks. This article for the first time presents an approach called Tiler to manage SMR disks by dividing the physical space into small autonomous regions (ARs). Each AR can manage its space allocation, address mapping, and cleaning independently. By managing these ARs in a log-structured way, RMWs can be avoided; besides, ARs can also help update data when the adjacent tracks contain no valid data. Tiler is capable of partitioning a large-scale cleaning into self-contained-small-scale cleaning and thus, the data that need to be relocated are limited inside independent ARs, which further minimizes the performance overhead. Our experimental results show that Tiler can shorten the overall system response time by 50.21 percent and reduce the cleaning time by 90.24 percent on average.

Motion estimation (ME) is a high efficiency video coding (HEVC) process for determining motion vectors that describe the blocks transformation direction from one adjacent frame to a future frame in a video sequence. ME is a memory and computation consuming process which accounts for more than 50% of the total running time of HEVC. To conquer the memory and computation challenges, this paper presents ReME, a highly paralleled processing-in-memory (PIM) architecture for the ME process based on resistive random access memory (ReRAM). In ReME, the space of ReRAM is mainly separated into storage engine and ME processing engine. The storage engine is used as conventional memory to store video frames and intermediate data, while the computation operations of ME are performed in ME processing engines. Each ME processing engine in ReME consists of Sum of Absolute Differences (SAD) modules, interpolation modules, and Sum of Absolute Transformed Difference (SATD) modules that transfer ME functions into ReRAM-based logic analog computation units. ReME further cooperates these basic computation units to perform ME processes in a highly parallel manner. Simulation results show that the proposed ReME accelerator significantly outperforms other implementations with time consuming and energy saving.

U-net deep neural network has shown good performances in medical image segmentation analysis. Most of the existing works are a single use of upsampling algorithm or deconvolution algorithm in the expansion path, but they are not opposites. In this paper, we proposed a U-net network optimization strategy, in order to use the available annotation samples more effectively. One deconvolution layer and upsampling output layer were added in the splicing process of the high-resolution features in the contraction path, and then the obtained “feature map” was combined with the high-resolution features in the contraction path in the way that broaden the channel. The training data used in the experiment is the pathological section image of prostate tumor. The average Dice scores for models based on our optimization strategy improve from 0.749 to 0.813. It proves that the deconvolution algorithm can extract feature information different from the upsampling algorithm, and the complementarity can achieve a better data enhancement effect.

As more and more scholars focus on cognitive intelligence, knowledge graph has been widely concerned. Because knowledge graph uses RDF to describe various resources, the storage and management of massive RDF data becomes a challenge. Existing methods are mainly based on relational database, RDF triples and graph model to store and query RDF data [1]. The method based on RDF triples is to build index according to (subject, predict, object) model. It is characterized by building multiple indexes to speed up the query, but it brings a great burden to the database storage. For example, RDF-3X constructs six three-dimensional indexes, six two-dimensional indexes and three one-dimensional indexes, uses a lot of storage space. At the same time, it uses the mapping dictionary to compress the storage space, which will slow down the query speed.To address the above issues, this paper proposes a lightweight and efficient method to store and query RDF data. Instead of mapping RDF data into a relational database or building an index based on RDF triples as most methods do, we develop a new index based on the Cuckoo Filter. In addition, the method of data block storage is adopted, which not only facilitates the storage management, but also makes the storage structure compact, and speeds up the data reading. At the same time, in order to ensure the uniqueness of the data in the index, we use the method of fingerprint value. Through comparative experiments on three large datasets, it is proved that our method improves the query performance by 450% over RDF-3X and 64% over gStore.

The write constraints of Multi-Level Cell (MLC) NAND flash memory make most of the existing flash translation layer (FTL) schemes inefficient or inapplicable. In this article, we solve several fundamental problems in the design of MLC flash translation layer. The objective is to reduce the garbage collection overhead to reduce the average system response time. We make the key observation that the valid pages copy is the essential garbage collection overhead. Based on this observation, we propose two approaches, namely, concentrated mapping and postponed reclamation, to effectively reduce the valid pages copy. Besides, we propose a progressive garbage collection that can well utilize the system idle time to reclaim more spaces. We conduct a series of experiments on an embedded developing board with a set of benchmarks. The experimental results show that our scheme can achieve a significant reduction in the average system response time compared with the previous work.