This article presents a 3.5-A unconditionally stable low-dropout (LDO) regulator. By optimizing loop pole placement and applying appropriate zero compensation, the LDO achieves unconditional stability across a wide output capacitance range of 0- 220 mu F and load current from 0 to 3.5 A. Fabricated in a radiation-hardened 0.18- mu m bipolar-CMOS-DMOS (BCD) process, the design incorporates multiple radiation-hardening-by-design (RHBD) techniques at both the circuit and layout levels, demonstrating total ionizing dose (TID) tolerance up to 300 krad(Si) and single-event latch-up (SEL) immunity with a linear energy transfer (LET) threshold of 76.5 MeV & sdot; cm2/mg. The regulator supports output voltages from 0.8 to 3.6 V and features a minimum dropout voltage of 154 mV at a load current of 3.5 A. It achieves a load regulation of 0.011%/A, a line regulation of 0.004%/V, and power supply rejections (PSRs) of -51 dB at 10 kHz and -40 dB at 1 MHz. Furthermore, a high-precision programmable current-limit protection circuit is integrated, allowing current-limit thresholds to be configured between 0.1 and 4.4 A.

This article presents an area-efficient high-precision Latching Current Limiter (LCL). A PMOS power transistor with priority‑voting substrate control is integrated on‑chip, eliminating reverse‑blocking body‑diode leakage while reducing the transistor area. High‑precision programmable current limiting is achieved via chopper offset‑stabilization in the current‑sensing amplifier, which cancels amplifier offset voltage and delivers a precision better than 4.2% over a 0.1 A–6 A range. The LCL also features comprehensive intelligent integration including soft‑start, reverse blocking, and fast trip‑off to suppress short‑circuit peak currents, as well as programmable current‑limit timing and reset timing, ensuring safe operating area (SOA) compliance. Operating from 1.7 V to 5.5 V, the LCL exhibits 28 mΩ on‑resistance at 3.3 V/6 A while occupying only 6.56 mm². Fabricated in a radiation‑hardened 0.18 μm BCD process incorporating multiple radiation-hardening-by-design (RHBD) techniques, it achieves total ionizing dose (TID) tolerance of 300 krad(Si) and single‑event latch‑up (SEL) immunity at an LET of 76.5 MeV·cm²/mg.

This article presents a model-free neural network (NN) controller design methodology based on transfer reinforcement learning (TRL) with Gaussian reward shaping, implemented and validated on a Buck switching converter under constant power load (CPL). A high stochastic training environment is constructed using behavioral CPL modeling and incorporates randomized variations in reference voltage, input voltage, and load power. The Gaussian reward function is rigorously designed via theoretical analysis of its gradient properties and convergence guarantees, with an asymmetric variant introduced to explicitly penalize overshoot and improve transient performance. Through a structured three-stage TRL framework, the optimal parameters of the reward function were systematically determined, significantly ensuring robustness within a dynamic training environment. Experimental results demonstrate robust performance under widely varying operating conditions and circuit parameters, confirming the effectiveness of the Gaussian reward formulation and the model-free learning approach. This research provides theoretical support and practical References for applying reinforcement learning (RL) to optimize complex operating conditions in power electronics.

Low dropout (LDO) voltage regulators using bipolar technology are widely applied in space applications due to their insensitivity to single-event latch-up (SEL) and significant current-handling ability. This study presents a bipolar LDO regulator designed for space missions, featuring a 7.5 A load current, 0.5% output voltage accuracy, and low-dose-rate radiation-hardened performance. To enhance the chip's low-dose-rate radiation hardening capability, a novel buried-structure lateral PNP (LPNP) transistor is applied. The buried LPNP transistor developed by us exhibits a higher current gain, which helps reduce quiescent current, improve the LDO's loop gain, and enable fast transient response, high-accuracy output voltage regulation, and low power consumption. Additionally, a distributed driving circuit combined with parasitic resistance-aware V VBE matching is proposed for multi-cell power transistors to achieve load current balancing in high-power transistors and enhance load current capability. Furthermore, a segmented high-order temperature compensation technique for the bipolar bandgap reference is developed to minimize the LDO's output voltage temperature drift. Test results show that, prior to irradiation, the bipolar LDO chip has a quiescent current of 300 mu mu A, a minimum input-output voltage difference of 600 mV, an output voltage temperature drift of 3.8 ppm/degrees C, a line regulation of 0.1 mV/V, and a load regulation of 0.3 mV/A. Radiation test results indicate that the LDO chip's low-dose-rate radiation resistance exceeds 300 krad(Si). Moreover, the device demonstrates robust SEL and single-event transient (SET) immunity, with a linear energy transfer (LET) level exceeding 99.8 MeV cm2/mg.

The sensors within aircraft engines are typically installed on stationary components. Monitoring the power takeoff (PTO) shaft is critical for flight safety. However, deploying battery-powered sensors on this component poses significant challenges due to its extremely high rotational speeds and exposure to temperature-varying environments. This work proposes a segmented electromagnetic energy harvester (SEMEH) with a self-powered maximum power point tracking (MPPT) circuit, addressing critical limitations of conventional battery-powered solutions. The SEMEH employs a novel dual-coil architecture, where the main coil directly powers sensors, while the subcoil energizes the MPPT circuit and provides dynamic voltage References. The subcoil-driven MPPT circuit adapts dynamically to variations in rotational speed and temperature, maintaining proportionality between main/subcoil voltages for real-time optimization. This enables the MPPT circuit to quickly identify the maximum power point (MPP) under variable temperature (1200-3000 r/min) and rotational speed (20 degrees C-80 degrees C) conditions. Compared to traditional MPPT methods, this self-feedback topology eliminates the need for complex calibration procedures, thereby enhancing the simplicity and reliability of the system. Experimental validation demonstrates a tracking response of 0.28 ms with <= 5% MPP offset and 1814.6-mW harvested power (74.2% peak efficiency). This work paves a new path toward providing battery-free and maintenance-free solutions for monitoring in aerospace or high-speed rotating machinery.

The voltage reference maintains excellent stability against process, supply voltage, and temperature (PVT) variations, rendering it a key component in power management systems. This paper presents a radiation-hardened bipolar voltage reference with a wide input range and low temperature drift for space applications. Designed and fabricated using a radiation-hardened bipolar process, the proposed voltage reference features strong radiation resistance, ensuring long-term stable operation while maintaining high precision. By adopting high-order compensation techniques, it achieves outstanding low-temperature drift performance. The voltage reference exhibits a temperature coefficient of 1.491 ppm/°C, with a voltage fluctuation of only 1.775 mV over an input voltage range of 3 V to 18 V. After exposure to a total ionizing dose (TID) of 300 krad(Si), its temperature coefficient increases to 1.752 ppm/°C, and no significant degradation of the reference voltage is observed.

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With the continuous development of synthetic aperture radar (SAR) jamming technology, low-power maneuvering repeater jammers are now flexible and can be located on multiple unmanned aerial vehicles (UAVs) and unmanned vehicles (UVs) at the same time, which greatly increases the difficulty of the anti-maneuvering repeater jamming method for spaceborne SAR. Due to the low-power transmission, the locations of the low-power repeater jammers and the protected areas in the imaged swath are relatively close in distance, while the transmission delay of the jamming is approximately equal to the pulse repetition interval (PRI). According to this phenomenon, an anti-maneuvering repeater jamming method using up- and down-chirp modulation is proposed in this paper. After alternately transmitting up- and down-chirp modulation signals, echoes of the jamming and the protected area are recorded in the same location within the echo-receiving window and are related to different chirp modulations. To remove the jamming echoes, de-chirping and frequency filtering are adopted after echo data segmentation. With jamming interference removal using frequency notch filtering, parts of the spectra corresponding to the desired echoes of the imaged swath are simultaneously removed. To recover the unwanted removed range spectra, linear prediction is introduced to improve the focusing quality. Finally, simulation results on both point and distributed targets validate the proposed anti-maneuvering repeater jamming method by using up- and down-chirp modulation.

Vehicles dissipate kinetic and potential energy over speed bumps. This wasted energy has immense potential for powering wireless sensor networks and intelligent transportation terminals. A hydraulic-based rotary electromagnetic energy harvester for road speed bump is proposed to recycle this mechanical energy. The vertical force from the vehicle passing over a speed bump is converted into horizontal motion through the transmission mechanism. And the fluid within the hydraulic cylinder is driven by the transmission mechanism to flow cyclically in the pipeline. Impeller of the electromagnetic generator is rotated by the high-speed flow of fluid, thereby generating electrical energy that can be stored in super capacity. Compact design is adapted to effectively utilize the internal spatial characteristics of the speed bump and minimizes damage to the road surface. An experimental testing was introduced using motor-controlled equipment to investigate the effects of different loading speeds and device pipe diameters on the output energy of the energy harvester. The optimum load for the harvester was determined to be 280 ohms at a rocker loading speed of 21 r/min, resulting in an output power of 0.35W.

This paper presents a wide input and low power LDO with fast transient response for automotive electronic applications. This design employs impedance adaptive compensation and load pseudo-ESR zero tracking techniques, achieving excellent frequency and transient performance over a wide load range. The LDO chip is fabricated in a $0.18 \mu \mathrm{~m}$ BCD process. The measurement results show the input voltage range is from 3 V to 45 V, and the output voltage range is from 1.22 V to 5 V with a quiescent current of $3.1 \mu \mathrm{~A}$. The load regulation is 0.07 $\mathrm{mV} / \mathrm{mA}$ with the load steps from 1 mA to 300 mA. The power supply rejection ratio of the chip are 80 dB at 10 kHz and 20 dB at 1 MHz.

Synthetic aperture radar (SAR) typically transmits a linear frequency modulation (LFM) waveform. It utilizes weighted windowing to depress the peak-to-sidelobe ratio (PSLR), which results in a decrease in signal-to-noise ratio (SNR). In contrast, a nonlinear frequency modulation (NLFM) signal can reconstruct the power spectral density (PSD) to achieve lower sidelobes without compromising the SNR. Considering the substantial challenges posed by hardware constraints in the real-time generation of complex NLFM waveforms, this letter proposes a piecewise linear (PWL) algorithm to optimize resource utilization while realizing parallel processing via pipeline execution and the Horner method. Meanwhile, an improved predistortion approach integrated with the PWL algorithm is utilized to compensate for the phase errors in the SAR system. The high-level synthesis (HLS) technique is applied in the waveform generator based on the radio frequency system-on-chip (RFSoC). The performance of the proposed method is validated through simulations, and practical experiments are conducted on an X-band airborne SAR system.

This paper investigates a real-time process generator of wideband signals, which calculates waveforms in a field-programmable gate array (FPGA) using the high-level synthesis (HLS) method. To obtain high-resolution and wide-swath images, the generator must produce multiple modes of large time-bandwidth product (TBP) linear frequency modulation (LFM) signals. However, the conventional storage method is unrealistic as it requires huge storage resources to save pre-computed waveforms. Therefore, this paper proposes a novel processing approach that calculates waveforms in real-time based simply on parameters such as the sampling frequency, bandwidth, and time width. Additionally, this paper implements predistortion through the polynomial curve to approximate phase errors of the system. The parallelizing process in the FPGA is necessary to satisfy the high-speed requirement of a digital-to-analog converter (DAC); however, repeatedly multiplexing real-time calculation consumes extensive logic and DSP resources, potentially exceeding FPGA limitations. To address this, this paper proposes a piecewise linear algorithm to conserve resources, which processes the polynomial only once, acquires the difference in two adjacent values through the register and pipeline, and then adds this increment to facilitate parallel computations. The performance of this proposed generator is validated through simulation and implemented in experiments with an X-band airborne SAR system.

This study introduces an all-digital delay-locked loop (ADDLL), which generates 20 evenly-spaced-phase clock signals. A successive-approximation register (SAR)-based dual-loop control is used to realize the locking process of the ADDLL. A modified SAR unit combined with a tri-state digital phase detector (TSDPD) is adopted to achieve a closed-loop operation of the ADDLL. A delay matrix, which can significantly reduce the jitter accumulation, is used to generate evenly spaced phases without using a long-cascaded delay line. Additional harmonic-lock detector circuits are added to the two control loops to avoid the harmonic lock issue. The ADDLL is designed and fabricated using a 0.18μm mixed-signal CMOS technology with an active area of 0.109 μm2. The lock range of the ADDLL is 30–230 MHz and the power consumption of the ADDLL is 8.9 mW at 100 MHz. The measured rms jitter is 23.3 ps at 100 MHz, and the results show a good linearity of the multiphase outputs at a 100 MHz input clock where the maximum DNL and INL are 0.08 and -0.22 LSB, respectively. The proposed ADDDLL is highly suitable for low-frequency, low-power, and high-time-resolution applications.

This paper presents a 7-phase switched capacitor converter with maximum power point tracking (MPPT) for piezoelectric energy harvester. The switched capacitor converter achieves the fractional open-circuit voltage MPPT method by reconstructing the capacitor array according to the appropriate voltage conversion ratio (VCR) to improve the mechanical energy harvesting efficiency in complex scenarios. The 7-phase switched capacitor converter designed in this paper can achieve voltage conversion ratios of 1/5, 1/3, 2/5, 1/2, 3/5, 2/3, and 4/5. Designed the switched capacitor converter in a 180 nm CMOS process. The simulation result shows when the vibration frequency changes, the overall efficiency of the proposed circuit can reach 80.66%.

To improve the dynamic performance, this paper proposes a dual-mode digital controller with a high accuracy load current estimator and Gaussian adaptive duty cycle switching for DC-DC buck converters with an auxiliary power stage. The proposed digital controller has two operating modes: steady state and transient. In steady-state mode, a conventional PID control module is used to regulate the main power stage and the output voltage. In transient mode, a charge balance control module is responsible for controlling the auxiliary power stage to improve the dynamic performance. A long short-term memory (LSTM)-based load current estimator is proposed to obtain high accuracy load current. It employs a multiple-to-one structure and estimates the load current based on time series data (a sequence of data points indexed in time order). A Gaussian adaptive duty cycle switching is proposed to suppress the output voltage chattering when transitioning between the auxiliary and the main power stages. Simulation and experimental results demonstrate that the proposed controller has a superior dynamic performance when compared to controllers using linear-based load current estimator and direct duty cycle switching. The overshoot/undershoot and settling time can be reduced by over 50 % for a 1.9 A load transient in a 5 to 1.8 V buck converter operating switching at 2 MHz..

A programmable digital controller for DC-DC switching converters has the advantages of strong versatility and high stability. In this paper, a programmable System on Chip (SoC) of digital controller is designed for applying to more switching converters topologies. Based on ARM Cortex-M0 processor, this digital controller SoC includes three error amplifying analog-to-digital converters (EADC) with 6 bits, four DPWMs with 250ps resolution, three PID control loops, and some digital peripherals that can achieve real-time monitoring, peripheral configuration, and management communication functions. Fabricated in a 110nm CMOS process. The experimental results show that by reasonably configuring the parameters of the registers, this chip can control a full bridge converter to achieve the design requirements, which proved strong versatility of this chip.

The impacted-type piezoelectric energy harvesters (IPEHs) are widely used to harvest theenergy of low-frequency impact forces from raindrops, human motion, machines, and otherenvironmental sources. Owing to the typically low impact frequency, the output voltagebetween the two excitations undergoes damping. The attenuation coefficient lambda, which reflectsthe damping rate, directly affects the performance of the energy harvesting circuit. This studyanalyzes and compares the variations of three energy harvesting circuits: full-bridge rectifier(FBR), parallel synchronized switch harvesting on inductor (P-SSHI), and synchronouselectrical charge extraction (SECE) circuits under varying lambda. First, the ideal energies of thethree energy harvesting circuits during one impact event are summarized according to theirmaximum output power per half-cycle related to lambda. Derivations of the IPEH with self-poweredFBR, P-SSHI, and SECE circuits are provided, including the energy consumption and start-upvoltage. Furthermore, these self-powered circuits connected with an IPEH are simulated. Theoptimal load resistance and capacitance of these circuits are analyzed relative to the variation of lambda.The optimal load resistance of the SECE circuit varies significantly as lambda increases, whereasthe optimal loads of other circuits remain relatively constant. The output energies of the threeself-powered circuits are analyzed as the force intensity and lambda vary. The P-SSHI circuit yieldsthe highest energy when appropriate components are selected. Under large lambda or weak externalforces, the output energy of the FBR circuit surpasses that of the SECE circuit. Finally, the threeself-powered circuits are implemented in the IPEH. The experimental results show that theself-powered P-SSHI circuit generates the highest energy, with the figure of merit graduallyincreasing with the external force, which is consistent with the theoretical analysis. Theguidance provided in this study is a reference for designing IPEH circuits.

Generally, synthetic aperture radar(SAR)generates linear frequency modulation (LFM) signals by method of look-up table (LUT), which requires calculating different LFM signals and storing these waveforms in advance. With the demand for multi-mode, high-resolution and wide swath of airborne SAR systems, the method of LUT is not available, because that requires huge storage resources. In order to solve these drawbacks in limited hardware resources, this letter proposes a novel LFM signal generator in real-time processing. By taking advantage of high level synthesis (HLS) on FPGA, the proposed generator calculates the LFM signal simply using parameters of pulse width, bandwidth, and sampling frequency. Meanwhile, in order to compensate for the SAR system phase error, the proposed generator calculates phase error using a linear polynomial algorithm, which can compensate for the phase error in real time. The simulation results prove that this approximation can achieve a good effect. The performance of this method is implemented by experiments with an X-band airborne SAR system.

Perovskite solar cells (PSCs) are popular light-to-electric energy converters thanks to their high power conversion efficiency and ease of manufacture. However, the hysteresis associated with the characteristics of PSCs has become a new challenge for energy harvesting technology. This paper presents a PSC model that adequately reflects the hysteresis and investigates the impact of the hysteresis on two maximum power point tracking (MPPT) methods. Oscillation caused by hysteresis occurs when the PSC is connected to an MPPT-controlled load. By overcoming this disadvantage, the incremental conductance algorithm performs better because it takes 78.6% less time to reach the maximum power point (MPP) than the perturbation and observation algorithm.

A low-noise and low-power front-end readout ASIC for CZT detectors has been designed and implemented in this work. This front-end readout ASIC has the characteristics of low noise, large input range, high accuracy and low power consumption, and is especially suitable for portable X/γ-ray spectrometers. The ASIC has been implemented using a $0.18\mu\mathrm{m}$ CMOS process. The test results indicate that, the input energy range is 0~8fC, the nonlinearity of gain is less than ±6%, the equivalent noise charge (ENC) for zero capacitance is only $147\mathrm{e}^{-}$, and the static power consumption is less than 2.5mW/ channel.