Deep learning-based side-channel attacks have advanced rapidly, yet most rely on single-path models with single-dimensional perception, poor robustness, and practical performance bottlenecks. This paper presents a novel side-channel analysis method using a multi-path autoencoder architecture and guided interference suppression training, focusing on architectural innovation over conventional optimization. We build dual complementary views (raw original view and convolutional autoencoder enhanced view) processed by parallel branches. An interference suppression training mechanism penalizes high-confidence wrong key guesses for clearer decision boundaries. A lightweight trace-level alternating fusion strategy combines outputs without extra parameters. Experiments on six public datasets show our method outperforms baselines, reducing required traces by up to 48% on masked implementations. Ablation studies verify each core component, and the framework is lightweight and plug-and-play.

This paper presents a single-inductor dual-output (SIDO) buck-boost converter featuring a novel regulation strategy based on dynamic energy allocation. This strategy effectively mitigates the severe cross-regulation interference inherent to traditional SIDO topologies, enabling the system to maintain robust stability under asymmetric load conditions. Furthermore, to address the risk of sub-harmonic instability induced by low-ESR ceramic capacitors, an on-chip active ripple injection technique is introduced to enhance feedback signal quality without requiring external RC components. Fabricated in a standard 0.18-μm Bipolar-CMOS-DMOS (BCD) process, the proposed chip occupies an area of 3.094 mm2 and can generate simultaneous positive and negative voltage rails. Measurement results demonstrate that the converter achieves a peak efficiency of 90.2% and a maximum output power of 18 W, alongside a worst-case cross-regulation of 0.09 mV/mA.

Vertically dominant heat flow in three-dimensional stacked chiplet systems (3D SCSs), driven by high heat flux density, induces severe hotspots and pronounced temperature non-uniformities, posing critical challenges to performance stability and long-term reliability. Transient thermal characterization thus requires accurate and fast simulation coupled with analysis of heat conduction mechanisms. To address this, we propose a unified framework integrating an explicit 3D general high-order finite difference (GHOFD) method with cone-fused heat flux streamlines (CFHFSs). The GHOFD method achieves a numerical error of less than 0.01 degrees C relative to the analytical solution. It demonstrates a computational speedup of more than 50x compared to the state-of-the-art alternating direction implicit (ADI) method. Applied to two representative 3D SCS models under Dirichlet and Robin boundary conditions, the framework reveals an inherently anisotropic and spatially non-uniform thermal behavior, dominated by vertical conduction yet modulated by the chiplets' layout and power distribution. The CFHFS elucidates 3D thermal behavior through qualitative streamline attributes (e.g., density, deflection) and cone size proportional to local heat flux magnitude. This integrated approach not only predicts thermal behavior with high accuracy and speed but also reveals the underlying 3D heat conduction mechanisms, offering actionable insights for thermal design, thermal analysis, and thermal management of next-generation heterogeneous chiplet systems.

In zoom analog-to-digital converters (ADCs), due to the dynamic updating and scaling of fine reference voltages by coarse SAR ADC, traditional noise coupling technique cannot be directly applied to fine Delta Sigma modulator, which may lead to modulator overload and a sharp decline in the signal-to-noise distortion ratio (SNDR). To address this issue, this article proposes a noise-coupled technique specifically designed for zoom ADCs. It establishes a mathematical model and determines the appropriate feedback voltage based on coarse quantization and the over-ranging factor, ultimately enhancing SNDR and energy efficiency. The zoom ADC is designed using a 180nm CMOS process and incorporates two integrators to achieve 3 rd-order noise-shaping capability (60 dB/dec). It achieves an SNDR of 105.7 dB at a sampling frequency of 256 kHz and an oversampling rate of 128, with a power consumption of only 90.25 mu W. The SNDR-based Schreier figure-of-merit (FoMs) is 176.1 dB, indicating competitive performance in terms of high resolution and energy efficiency.

Scenario-based testing is the dominant approach for validating autonomous driving systems (ADS) through simulation. However, generating critical scenarios that effectively uncover real defects in ADS while managing the complexity of the generation remains a challenge. This paper introduces CCTest, a test framework that generates critical test data using simple scenarios decomposed from complex ones and provides qualitative analysis of the scenarios. CCTest ensures that any safety violation observed indicates a defect in the tested autopilot by creating situations where each vehicle is controlled by the autopilot under test and has a feasible safety policy. Evaluations have shown that CCTest effectively revealed major defects in Apollo, Autoware, and the built-in autopilots in Carla and LGSVL simulators. CCTest also outperforms existing tools in efficiently uncovering real defects in autopilots.

Testing autonomous driving systems (ADS) presents significant challenges in trajectory planning, route control, and collision avoidance, particularly at complex junctions. Among these, irregular junctions are especially valuable for exposing ADS weaknesses—yet they remain difficult to generate systematically. Since manually configured irregular junctions may not accurately reflect real-world conditions, a more practical approach is to identify existing irregular junctions. This paper presents a method for extracting irregular junctions from global OpenStreetMap (OSM) data and generating safety-critical scenarios based on them. By analyzing junction topologies and quantifying them with a difficulty metric, our approach uncovers challenging scenarios that effectively expose ADS defects. Experimental evaluations with various autopilots show that the identified junctions and generated scenarios trigger unique ADS defects more effectively than simulator-provided ones.

Despite extensive research, the testing of autonomous driving systems (ADS) landscape remains fragmented, and there is currently no basis for an informed technical assessment of the importance and contribution of the current state of the art. This paper attempts to address this problem by exploring two complementary aspects. First, it proposes a framework for comparing existing test methods in terms of their intrinsic effectiveness and validity. It shows that many methods do not meet both of these requirements. Either because they are based on criteria that do not allow for rapid, inexpensive, and comprehensive detection of failures, or because the degree of validity of the properties tested cannot be accurately estimated. In particular, it is shown that most critical test methods do not take into account the nominal operational capabilities of autopilots and generate scenarios that are impossible for the tested vehicles to handle, resulting in unjustified rejections. Secondly, the paper shows that test effectiveness and validity are highly dependent on how autopilots are designed: how they choose between different control policies to perform maneuvers, as well as on the reproducibility of the results. In fact, most test methods take for granted two principles underlying traditional methods, but do not generally apply to ADS. We maintain that the absence of rationality and determinacy significantly impairs the effectiveness and validity of test methods, and provide test results on eight open autopilots, in which most do not satisfy these properties, thereby illustrating this fact. We conclude that under the current state of the art, it is impossible to obtain strong enough guarantees for essential autopilot properties and recommend that autopilots be developed with a view to both rationality and determinacy.

This paper presents a high-precision remote temperature-sensing chip designed for advanced computing systems that require high-precision thermal management. The parasitic resistance, beta compensation, and early voltage compensation are proposed to achieve accuracy compensation of remote temperature sensing, whether using discrete transistors or parasitic transistors. The chip completed the circuit and layout design in a 0.18 μm CMOS process, with a chip area of 0.33 mm2 and a supply voltage of 1.8 V. Post-layout simulation results showed that the chip achieves a temperature-sensing accuracy of ±0.25 °C within the temperature range of −55 °C to 125 °C when adopting discrete transistors and parasitic transistors for remote temperature measurement.

To address the challenges of dynamic range and accuracy in sensor interface circuits, this paper proposes an instrumentation amplifier (IA) utilizing common-mode rejection enhancement, featuring a wide input common-mode range (ICMR) and a high common-mode rejection ratio (CMRR). The design employs a three-operational amplifier structure with precise current feedback loops and integrates a specialized common-mode feedback circuit to dynamically suppress common-mode signals from the front-end sensor. The design is fabricated using complementary bipolar technology. Measurement results showed that the ICMR reaches up to 56.5 V, the CMRR achieves up to 114 dB, and the gain accuracy is less than 0.01% across the 1–1000 gain range, with a gain-bandwidth product of 3.3 MHz.

To address the challenges of system integration under extreme thermal and micro-vibration conditions in the space environment, this paper proposes a high-reliability microsystem integration design methodology tailored for complex space applications. The core approach involves utilizing multiple simulation tools for multi-physics analysis—mechanical, thermal, and electrical — and reliability-driven optimization to establish a comprehensive design framework for System-in-Package (SiP) modules. Additionally, a multi-faceted, multi-chamber heterogeneous integration structure based on high-temperature co-fired ceramics (HTCC) is employed to achieve heterogeneous integration of chips fabricated with different process technologies. This design significantly reduces the microsystem’s weight and size while enabling system reliability assessment through simulation-driven process optimization. Currently, the developed product has been successfully implemented in mass production, validating the engineering practicality of the simulation methodology and the integrated design optimization process.

The significant thermal challenges faced by the new generation of high-density integrated microsystems have become hot research topics in current thermal design, management, and reliability of microsystems. The non- uniformity of temperature field (NUTF) is at the core of these challenges. Accurately characterizing the NUTF of microsystems has been a difficult task. This paper proposes an accurate characterization method for micro- system NUTF based on singular value decomposition (SVD) to enhance the effectiveness and accuracy of traditional NUTF characterization methods. The paper also investigates the impact of the non-uniform distribution of the microsystem's heat flux densities (HFDs) on the temperature field and its complexity using the singular value properties. The results demonstrate that the proposed method can quantitatively characterize the steady-state NUTF and the spatial-temporal transient NUTF of the microsystems. The decay rate of the singular values can effectively identify the non-uniformity of the microsystem's HFDs. The number of singular values above a threshold can quantitatively assess the complexity of the microsystem temperature field.

Microsystems face challenges such as high heat flux density and localized hot spots in the temperature field, which significantly impact their thermal reliability. The method for thermal characterization of the temperature field forms the foundation for studying the thermal reliability of microsystems. Accurately and comprehensively characterizing the temperature field is a challenging problem in current research. In this scholarly article, we present a viable approach for characterizing the steady-state and transient heat conduction mechanisms of microsystems. We introduce two new thermal characterization parameters: the gradient mode, which can more clearly characterize the magnitude of the gradient value and quantitatively analyze the spatial position of the temperature field change in the microsystem, and the heat flux direction factor (HFDF), which can effectively characterize the temporal and spatial variation characteristics of the transient temperature field. It can dynamically display the conduction process of heat flow in the temperature field, providing an effective means for revealing the heat conduction mechanism of the microsystem.

Microsystems face challenges such as high heat flux density and localized hot spots in the temperature field, significantly impacting their thermal reliability. Accurately and comprehensively characterizing the temperature field is a challenging problem in current research. We present a general high-order finite difference (GHOFD) algorithm for the high-accuracy numerical solution of the two-dimensional transient heat conduction equations (THCEs). The 10th-order GHOFD algorithm is accurate up to 10(-7) degrees C. Secondly, we present a viable approach for characterizing microsystems' steady-state and transient heat conduction mechanisms. We introduce two new characterization parameters: the gradient modulus and the heat flux direction factor (HFDF). The gradient modulus can more clearly characterize the magnitude of the gradient vector and quantitatively analyze the spatial position of the temperature field change in the microsystem. The HFDF can dynamically display the heat conduction process in the temperature field. Finally, using temperature field simulation and microsystem characterization, we have validated the effectiveness of the proposed method and new parameters.

A design method of BJTs for high-precision temperature-sensing is studied. The effects of non-idealities in the BJT on temperature-sensing accuracy are analyzed, and an accuracy evaluation formula containing the non-idealities is derived. We have proposed a novel parameter criteria of high-precision temperature-sensing BJT which constrains the influenced error of each non-ideality below ±0.1 °C using the variable-controlling procedure. The conversion approach from the proposed parameter criteria to electrical characteristics is also developed to guide the high-precision temperature-sensing BJT design. According to the proposed method, temperature-sensing BJTs are designed and fabricated. The test results showed that the temperature-sensing accuracy is within ±0.5 °C in temperature range of −55 °C to 125 °C, which meets the need for high-precision temperature sensing.

A temperature sensor plays an important role in modern high-performance processing chips. A temperature sensing core with a high sensing accuracy is proposed in this article to meet the increasing demand for on-chip thermal monitoring. A comprehensive analysis of the thermal characteristics in subthreshold current is presented to achieve optimal sensing accuracy. The thermal information contained in subthreshold current is converted into a frequency which can be easily digitized in processing chips. The dynamic offset compensation (DOC) method is proposed to improve the supply sensitivity. In addition, small area and low power are also achieved due to its simple structure and low working current. The sensor is designed and implemented in the standard 0.153-mu m CMOS technology. After a two-point calibration and systematic error removal (SER), the proposed sensor has a measuring inaccuracy of+0.57(degrees)C/-0.65(degrees)C (3 sigma) within the temperature range of-40(degrees)C similar to 120(degrees)C. The occupied area and power consumption of the sensor are only 860 mu m2and 1.3 mu W, respectively. With the help of DOC, the sensor can achieve a supply sensitivity of 2.1(degrees)C/V. This combination of high accuracy, small area, and low energy consumption makes this sensor suitable for on-chip dense thermal monitoring applications

A high-accuracy fully integrated temperature sensor for a wide temperature range up to 150 degrees C is presented in this article. The sensing circuits with the asymmetric operational amplifier and bias current optimization is applied to eliminate the component mismatch error and enhance the accuracy. The asymmetric operational amplifier can remove the offset voltage avoiding the switching noise compared with the chopping method. An extended counting analog-to-digital convertor (ADC) is proposed as the readout interface due to its compact structure and high efficiency. An easily-achieved dynamic range improvement is devised. Benefited by the dynamic range improvement, the 14-bit ADC can achieve a resolution of 0.0156 degrees C. This temperature sensor is fabricated in a 0.18-mu m CMOS process, and it achieves an accuracy of +/- 0.4 degrees C (3 sigma) from -55 to 150 degrees C.

The three-operational amplifiers (three-opamp) structure is a widely used topology to design precision instrumentation amplifiers (IAs). However, the input common-mode range (ICMR) of the classical three-opamp IA is limited to the output voltage range of the internal operational amplifiers, resulting in the output voltage range being constrained by the input common-mode voltage. This article proposes an ICMR-enhanced three-opamp topology, which constructs a common-mode feedback (CMFB) loop at the first stage of the IA, enabling the first stage has the capability of common-mode rejection. Hence, the proposed ICMR-enhanced three-opamp IA overcomes the limitation of ICMR, eliminates the constraint of the output voltage range and improves the common-mode rejection ratio (CMRR). The proposed circuit was designed and simulated using complementary bipolar process. The simulation results showed that the output voltage range remains constant regardless of the input common-mode voltages, the CMRR is greater than 150 dB, and the Gain Bandwidth Product (GBW) was 4.1 MHz. The advantages of the proposed ICMR-enhanced three-opamp IA will enable its use in more environments.

A low power dynamic-distributing-bias CMOS temperature sensor is presented for temperature-sensing RFID tag. To reduce the chip area and power consumption, we propose a new hybrid PTAT/REF current generator. A new current-mode readout scheme is devised, which is dedicated to improve the dynamic range utilization of ADC and further reduce the power consumption. Fabricated in 0.153 mu m CMOS process, the sensor shows a measured inaccuracy of-0.6 degrees C to +0.8 degrees C from -40 degrees C to 125 degrees C. This performance is obtained by using precision and nonlinearity compensation techniques such as VBE trimming, ratio-metric curvature correction, chopping and dynamic element matching (DEM). The sensor has low power consumption of 2.21 mu W under a 1.6 V supply and occupies an area of 0.07 mm(2).

This article presents a third-order, feedforward, single-bit Delta-Sigma analog-to-digital modulator (DSM) based on an output swing-enhanced gain-boost inverter for low-voltage low-power applications such as wearable devices, mobile health, and the Internet of Things (IoTs). The proposed output swing-enhanced structure addresses the output-swing reduction in the conventional structure while achieving high DC gain and large output swing simultaneously. Implemented in a 180 nm CMOS process, the entire chip is comprised of a delta-sigma modulator, an oscillator, and a current reference. It achieves 86.1 dB peak SNR and 92 dB dynamic range (DR) with 1.95 kHz signal bandwidth. The whole chip dissipates 54.5 μW, leading to a 167.6 dB Schreier Figure of Merit (FoMs).