A slope analog-to-digital converter (ADC) amenable to be fully implemented on a digital field programmable gate array (FPGA) without requiring any external active or passive components is proposed in this paper. The amplitude information, encoded in the transition times of a standard LVDS differential input—driven by the analog input and by the reference slope generated by an FPGA output buffer—is retrieved by an FPGA time-to-digital converter. Along with the ADC, a new online calibration algorithm is developed to mitigate the influence of process, voltage, and temperature variations on its performance. Measurements on an ADC prototype reveal an analog input range from 0.3 V to 1.5 V, a least significant bit (LSB) of 2.6 mV, and an effective number of bits (ENOB) of 7.4-bit at 600 MS/s. The differential nonlinearity (DNL) is in the range between −0.78 and 0.70 LSB, and the integral nonlinearity (INL) is in the range from −0.72 to 0.78 LSB.

This paper presents a 19 ps precision and 170 M samples/s time-to-digital converter (TDC) in FPGA. Through the direct count method and tapped delay line method, the coarse count and fine count can be extracted, respectively. The direct count is realized by the 350 M clock and the tapped delay line is constructed by the CARRY4 block. The ones-counter encoder is used to convert the thermometer code with bubble errors into binary code, which is applicable to all the FPGA chips. This work not only explains the schematic of the ones-counter encoder, but also shows how to configure it. Owing to the inconsistency of delay elements caused by process, bin-by-bin calibration is utilized to improve the differential nonlinearities (DNL) and integral nonlinearities (INL) of the TDC. A novel method was developed to compensate the influence of voltage and temperature. As the delay elements vary with voltage and temperature, a frequency counter is used to extrapolate and compensate its effect on the delay line. All of the above strategies use online calibration and improve the precision and sampling rate of TDC. The experimental results show the least significant bit (LSB) achieves 17.4 ps, the DNL is within [−0.90, 1.67] LSB, and the INL is in the range of [−1.90, 3.31] LSB.

With the high-density integration of chips, the use of multi-type SRAM memory is becoming more and more extensive, which also brings great challenges for the testing of chips. Traditional MBIST is usually also achieved by using EDA tools, which makes it difficult to test multi-type memory directly. In this paper, a two-layer FSM PMBIST test structure is proposed, with the outer FSM controls to cut the effective address and data, which can realise the efficient testing of multi-type memory, and the inner FSM combines LFSR and integrates the improved March LR algorithm, which can achieve 100% coverage of the static dual-cell coupling faults. Finally, the simulation of the 55nm process verifies the normal function and good performance of the test structure.

This paper presents a low jitter All-Digital Delay-Locked Loop (ADDLL) with fast lock time and process immunity. A coarse locking algorithm is proposed to prevent harmonic locking with just a small increase in hardware resources. In order to effectively solve the dithering phenomenon after locking, a replica delay line and a modified binary search algorithm with two modes were introduced in our ADDLL, which can significantly reduce the peak-to-peak jitter of the replica delay line. In addition, digital codes for a replica delay line can be conveniently applied to the delay line of multi-channel Vernier TDC while maintaining consistency between channels. The proposed ADDLL has been designed in 55 nm CMOS technology. In addition, the post-layout simulation results show that when operated at 1.2 V, the proposed ADDLL locks within 37 cycles and has a closed-loop characteristic, the peak-to-peak and root-mean-square jitter at 800 MHz are 6.5 ps and 1.18 ps, respectively. The active area is 0.024 mm2 and the power consumption at 800 MHz is 6.92 mW. In order to verify the performance of the proposed ADDLL, an architecture of dual ADDLL is applied to Vernier TDC to stabilize the Vernier delay lines against the process, voltage, and temperature (PVT) variations. With a 600 MHz operating frequency, the TDC achieves a 10.7 ps resolution, and the proposed ADDLL can keep the resolution stable even if PVT varies.

文章提出一种基于相位内插型时间数字转换器(time-to-digital converter,TDC)的补偿算法及校准电路,通过该电路能有效地解决由于亚稳态和PVT(process,voltage and temperature)因素变化引起的TDC的采样错误,并且不需要额外的计数器、锁频电路或基于统计方法学的复杂结构.基于该方法的TDC电路采用CMOS 0.110μm工艺设计实现,版图面积仅为380×140μm2,在1.2 V电源下功耗为4.2 mW.仿真结果表明:系统分辨率为104 ps,最大微分非线性(differential nonlinearity,DNL)和积分非线性(integral nonlinearity,INL)分别为0.3、2.5 LSB,证明依据该算法的TDC电路具有良好的时间精度和线性度.

The authors wish to correct the following errors in the original paper [...]

时间数字转换器(Time-to-Digital Converter,TDC)是一种将连续时间信号转换为数字信号输出的器件,是飞行时间(TOF)激光雷达中的关键部件.在利用计数器粗采样和多相位内插细采样的传统结构上,设计了一种基于相位内插的双级粗细结合型时间数字转换电路,并增加了双回波接收通路来接收多脉冲回波信号,在此基础上设计了一款17通道多路TDC系统芯片.芯片采用CMOS 0.11 μm工艺设计,版图面积为0.6 mm×3 mm.后仿真结果显示,在1.2 V电源下其功耗小于100 mW,单输入精度平均值为51.7 ps,动态范围为3.4 μm,且线性度良好.该TDC芯片适用于飞行时间脉冲激光雷达的信号计时.

In this paper, a high precision time digital converter(TDC) is designed based on FPGA and ARM, It includes coarse module, delay chain module, look-up-table module, ringosc moduleand spi module in the FPGA chip. The ARM chip is used for reading the timestamp and printing through the serial port. The key technology of this design is using the CARRY4 block of Xilinx Aritex-7 series to construct a delay chain for finecount. The system clock is used as the coarse count. The timestamp is obtained by the combination of fine time and coarse time.In addition, the precison of TDC is improved by code density test. The experiment result shows that precision of TDC is 43.2ps.

高精度脉冲式激光测距的精度与时间数字转换器（TDC）的精度密切相关,基于现场可编程门阵列（FPGA）的多通道TDC可有效降低系统的复杂度、提高测量效率。利用Xilinx Kintex-7系列内的CARRY4模块构造延迟链作为细计数,用25位200M的系统时钟进行粗计数,采用粗细结合的方式,在FPGA芯片内设计并验证了8通道高精度TDC。针对延迟单元的超前进位特性及其受温度电压影响的非线性时延,利用码密度测试法和在线校准法进行校准。实验结果表明,设计的8通道TDC分辨率小于35ps,精度为36.8ps,误差峰峰值为157.2ps,量程为167.77ms。