This paper presents a low jitter All-Digital Delay-Locked Loop (ADDLL) with fast lock time and process immunity. A coarse locking algorithm is proposed to prevent harmonic locking with just a small increase in hardware resources. In order to effectively solve the dithering phenomenon after locking, a replica delay line and a modified binary search algorithm with two modes were introduced in our ADDLL, which can significantly reduce the peak-to-peak jitter of the replica delay line. In addition, digital codes for a replica delay line can be conveniently applied to the delay line of multi-channel Vernier TDC while maintaining consistency between channels. The proposed ADDLL has been designed in 55 nm CMOS technology. In addition, the post-layout simulation results show that when operated at 1.2 V, the proposed ADDLL locks within 37 cycles and has a closed-loop characteristic, the peak-to-peak and root-mean-square jitter at 800 MHz are 6.5 ps and 1.18 ps, respectively. The active area is 0.024 mm2 and the power consumption at 800 MHz is 6.92 mW. In order to verify the performance of the proposed ADDLL, an architecture of dual ADDLL is applied to Vernier TDC to stabilize the Vernier delay lines against the process, voltage, and temperature (PVT) variations. With a 600 MHz operating frequency, the TDC achieves a 10.7 ps resolution, and the proposed ADDLL can keep the resolution stable even if PVT varies.
文章提出一种基于相位内插型时间数字转换器(time-to-digital converter,TDC)的补偿算法及校准电路,通过该电路能有效地解决由于亚稳态和PVT(process,voltage and temperature)因素变化引起的TDC的采样错误,并且不需要额外的计数器、锁频电路或基于统计方法学的复杂结构.基于该方法的TDC电路采用CMOS 0.110μm工艺设计实现,版图面积仅为380×140μm2,在1.2 V电源下功耗为4.2 mW.仿真结果表明:系统分辨率为104 ps,最大微分非线性(differential nonlinearity,DNL)和积分非线性(integral nonlinearity,INL)分别为0.3、2.5 LSB,证明依据该算法的TDC电路具有良好的时间精度和线性度.
时间数字转换器(Time-to-Digital Converter,TDC)是一种将连续时间信号转换为数字信号输出的器件,是飞行时间(TOF)激光雷达中的关键部件.在利用计数器粗采样和多相位内插细采样的传统结构上,设计了一种基于相位内插的双级粗细结合型时间数字转换电路,并增加了双回波接收通路来接收多脉冲回波信号,在此基础上设计了一款17通道多路TDC系统芯片.芯片采用CMOS 0.11 μm工艺设计,版图面积为0.6 mm×3 mm.后仿真结果显示,在1.2 V电源下其功耗小于100 mW,单输入精度平均值为51.7 ps,动态范围为3.4 μm,且线性度良好.该TDC芯片适用于飞行时间脉冲激光雷达的信号计时.
