Summary: Background: Parenteral nutrition (PN) is important to maintain adequate nutrition in patients who have a non-functioning gastrointestinal tract. Our aim was to characterise patients receiving PN initiated in the intensive care unit (ICU) or the general wards. Methods: Data from patients who received PN in two Australian hospital sites within a single health service between June and December 2016 (inclusive) was retrospectively collected. Demographics, cause for admission, indication and duration, and complications of PN were recorded. The latter included time to PN commencement, refeeding hypophosphataemia, biochemical liver dysfunction, hypoglycaemia and line sepsis. Results: Sixty-one patients received PN during this period. There was no delay between referral and commencing PN in ICU whilst seven (21.2%) ward patients were delayed by an average of 2.0 days (p = 0.01). Ward patients averaged 8.1 days of negligible oral intake compared with 4.3 days in ICU (p = 0.002). Complications were recorded in 19 (67.9%) ICU PN patients and 13 (39.4%) ward PN patients (p = 0.04). Refeeding hypophosphataemia was detected in three (9.1%) ward patients and six (21.4%) in ICU. There were eight (24.2%) cases of liver biochemical abnormality post commencing PN on the ward compared with 14 (50%) in ICU. There was no difference in hospital length of stay or survival between the groups. Conclusions: Patients receiving nutritional support initiated in the ICU were commenced on PN sooner than patients on the ward but experienced more complications. Ward patients experienced negligible oral intake for almost twice as long as ICU patients. Keywords: Parenteral nutrition, Intensive care unit, Ward, Malnutrition, Refeeding syndrome

提出了一种改进的遗传算法,该算法在求解划分问题的同时也解决了多种硬件方式探索问题.算法依据硬件实现方式的硬件延时-面积矛盾的特征,结合Q-学习算法和贪婪规则,自适应地选择合适变异方向,减少变异盲目性,增强遗传算法的局部搜索能力.实验结果表明,与BUB算法和标准遗传算法相比,本文方法在搜索质量、收敛性方面具有更好的效果.

To overcome the shortcoming of existing C2VHDL compiler dealing with pointer,based on the investigation of traditional algorithm,a block-based pointer analysis algorithm was designed and realized in the ASCRA compiler,which is developed for the application of CPU-FPGA based on LLVM.Experiment results show that this algorithm can simplify the pointer analysis process,meanwhile,achieve the same precision as the flow sensitive pointer algorithm.This algorithm also can support more pointer data types than pointer reduction technology.The VHDL programs generated by ASCRA using this algorithm can achieve the same resource consumption and processing speed as the pointer reduction technology.

Two-dimensional (2-D) convolution networks are widely used in pattern recognition and intelligent text applications. Depending on the size of input image and convolution kernel, the 2-D convolution can require significant amounts of calculation, thus suggesting that the actual operation is both compute-extensive and memoryextensive. Multiplyaccumulate (MAC) based Field-programmablegate-array (FPGA) parallel processing architectures were proposed to accelerate calculations for the 2-D convolution. And data buffering implemented with FPGA onchip resources was used to reduce the offchip memory bandwidth requirement. In this paper, we present a computation trade-off involved in mapping 2-D convolution networks on an FPGA device. Compared with the previous methods, the new scheme exhibits a good balance between computation resource and off-chip memory bandwidth utilization, and therefore is suitable for FPGA-based implementation. © 2013 ICIC International.

An adaptive image denoising method based on Empirical Mode Decomposition(EMD)is proposed to denoise image and hold the image details as many as possible simultaneously. Four one-dimension vectors are obtained by expanding the image with noise from the vertical, horizontal, left and right diagonal direction respectively. They are processed using EMD and all In-trinsic Mode Functions(IMFs)resulting from the decomposition of each one-dimension vector are denoised where the hard threshold local denoise method is employed and the proposed adaptive threshold based on the noise standard deviation is used. The de-noised IMFs are summed up. The four de-noised images are obtained by the inverse transform. The last de-noised image is achieved by calculating the mean of the four de-noised images. The experimental results show that the image with noise can be denoised and the details of the image hold effectively.

To aid in the hardware/software partitioning of the reconfigurable computing systems, it is necessary to conduct fast and accurate FPGA-based delay estimations before the partitioning. Most previous works predict the delay by adopting a high-level delay estimation based on empirical formulae. In such method, the empirical formulae are often obtained by a regression analysis on the real values reported by the synthesis and place-and-route tools of FPGAs. With alternative properties of tools or different FPGA devices, the empirical formulae need to be re-analyzed and decided. However, it is time-consuming due to inevitably repeated running synthesis and place-and-route tasks, which results in slow estimation and always beyond the tolerance of the estimation time. To address this problem, we present an improved high-level delay-estimation method in this article. We derived theory formulae called increasing formulae for HLL (High Level Language) operations from the basic idea of the hardware circuit design. These increasing formulae can be fit for most FPGAs. Combining the proposed formulae, the paper proposes a rapid estimation algorithm also. And the algorithm can obtain hardware delay of different hardware versions, thus reduces the number of times of running the time-consuming tasks greatly. Experimental results show that our method can achieve error within 2.69% for virtex-5 FPGA, compared with the real values.

To aid in the hardware/software partitioning of recon gurable computing systems, fast yet accurate FPGA based delay estimations are necessary before the partitioning. Most previous works predict the delay by using a high-level delay-estimation method of the empirical formulae. However, this method needs to run many times of the time-consuming synthesis, place and route procedures, which may take up to hours or days for all possible partition options. To address this problem, this paper proposed an auto estimation model to improve the previous high-level delay-estimation. In this model, we rstly derive calculation formulae called increasing formulae of HLL operations from the basic idea of the hardware circuit design. Then the feedback based framework is applied to adjust the increasing formulae for alternative FPGAs or synthesis properties, and estimate the delay of the partitioning. This model reduces the times of running the time-consuming procedures. Experimental results show the method can achieves error within 5% for virtex-5 FPGA, compared with the real delay. © 2013 Binary Information Press.

Convolution filtering applications range from image recognition and video surveillance. Two observations drive the design of a new buffering architecture for convolution filters. First, the convolutional operations are inherently local; hence every pixel of the output feature maps is calculated by the neighboring pixels of the input feature maps. Even though the operation is simple, the convolution filtering is both computation-intensive and memory-intensive. For real-time applications, large amounts of on-chip memories are required to support massively parallel processing architectures. Second, to avoid access to external memories directly, the data that are already stored in on-chip memories should be used as many times as possible. Based on these two observations, we show that for a given throughput rate and off-chip memory bandwidth, a rotation-based data buffering architecture provide the optimum area-utilization results for a particular design point, which are commonly used applications in recognition area.

为了较好地解决被部分遮挡的人脸的检测问题,提出一种基于组件距离匹配度函数的人脸检测方法.该算法首先采用基于支持向量机的Adaboost算法即AdaboostSVM算法对输入图像进行人脸各组件的检测,然后根据组件间距离的均值和方差构建组件距离匹配度函数,并提出基于组件距离匹配度函数的组件整合验证算法,在此基础上对被遮挡的组件的位置进行估计,进而实现部分遮挡的人脸的检测与定位.实验结果表明,该方法能够提高部分遮挡的人脸的检测性能与速度,能够在复杂背景下对被部分遮挡的人脸进行较为准确的定位与检测.

This paper presents an efficient parallel architecture for fast solving linear system of equations over binary operations of GF(2),which is derived from a proposed hardware-optimized Gaussian elimination.The optimization of the Gaussian elimination with pivot element is realized by using parallel elimination and cyclic shift operations instead of loop nest in each iteration.A mesh structure of "smart memory" cells is proposed for building the whole parallel architecture where the modified algorithm is mapped onto.The average running time of the architecture for n-dimension binary matrix equals 2n cycles as opposed to about 1/4n3 in software.Experimental results show that the performance of the system is improved by about two orders of magnitude.

The loop structure is always considered as the main time-consuming part in most computationally intensive applications.Since the FPGA-based reconfigurable computing systems emerge in recent years,the static techniques for analyzing loop structures are not able to meet the requirement of specific optimization according to the current behavior of programs.To address the lack of directly accessing the run-time information by using the dynamic techniques for analyzing loops,a new loop-analysis method is proposed.In this method which is implemented on the Low Level Virtual Machine(LLVM),the loop structures obtained from the Control Flow Graph(CFG)are recognized according to the dominating relationship,then the result of the edge profiling before the frequency of loop-calling,the average frequency of iteration and time of running are calculated.Experimental results manifest that the proposed method can recognize all the loop structure and collect the loop run-time information accurately,which can support hardware/software partitioning work of reconfigurable computing.

In this paper, we proposed a parallel hardware methodology employing the modified Gaussian elimination algorithm to efficiently solve linear system of equations (LSEs). Two parallel operators are issued in the hardware-optimized algorithm. Moreover, to be the proof-of-concept, the proposed parallel methodology is implemented to hardware structures in cases to address solving LSEs over GF(2) (primarily are bits operation) and LSEs with floating-point (IEEE-754 standard, 32-bit single precision) coefficient matrix. The corresponding hardware is mainly composed of uniformly distributed basic cells which store and register data, yielding a standalone worst case time complexity O(n 2) opposed to O(n 3) of the software replication. Finally, the given experimental result inosculated with the theory analysis.

The loosely-coupled reconfigurable computing model includes the host microprocessor in conjunction with an external stand-alone reconfigurable hardware which takes advantage of low cost in technology and development time. It can work as a fast emulation approach to study reconfigurable computing prototype system. One of the key features of such emulation system is the ability to perform the communication. In this paper, we proposed a high speed hardware channel with direct memory access(DMA) transaction method based on Xilinx ML555 development kit and PCI-express(peripheral component interconnection express) endpoint block IP. Experiments show that both read and write transaction speed in this design meet the theoretical maximum speed.

In order to decrease the maintenance cost of structure P2P network,and increase the efficiency of the route and quire,we proposed a low maintenance cost small-world P2P networks(LMCS),described the methods of network of the creating and maintenance.Small-world characteristic makes the better efficiency of the route and quire,and the clustering mechanism and extension of the COU strategy were used to decrease the maintenance cost.By Simulation,LMCS obviously presents the small-world characteristic.In contrast to Chord,LMCS has the lower maintenance cost and the higher query efficiency.

A method for face detection based on skin color segmentation and improved AdaBoostSVM algorithm was proposed.This method can improve the performance and speed of face detection.Skin color segmentation was implemented through the calculation of the similarity of skin color in YCgCr space.Then,the face regions of the candidate were obtained.An improved AdaBoostSVM algorithm was proposed to enhance the face detection accuracy according to the asymmetry of the face and non-face samples in face detection,and this algorithm was used to verify the face regions of the candidate.Experiment results show that the proposed algorithm enhances the performance and speed of face detection,and can detect face regions quickly and accurately with complex background.