Modern regulations [1] stress the necessity of testing integrated circuits (ICs) in order to determine the real level of their resistance to single voltage pulses induced by electromagnetic radiation (EMR). With expansion of the EMR spectral composition, however, direct energy release can occur due to the absorption of the EMR field energy by the IC chip itself. To assess this possibility, the relationship is found between different mechanisms of the EMR-induced energy release for the typical irradiation geometry.
Приведены результаты экспериментальных исследований образцов КМОП-микросхем CD4001BCN_NL на импульсную электрическую прочность (ИЭП) при двух значениях температуры окружающей среды +25 и +125°C. Анализ полученных результатов показал, что температура среды влияет на значения показателей импульсной электрической прочности исследуемой микросхемы. Величина и характер изменения ИЭП может быть описаны моделью теплового повреждения pn-перехода.
The results of the experimental studies of CD4001BCN-NL CMOS chips on the impulse electric strength (IES) at two ambient temperatures (+25°C and +125°C) are given. The analysis of the obtained results showed that the ambient temperature effects on the impulse electric strength indices of the studied chip. The value and behavior of the IES can be described by the p - n -junction thermal damage model.
Using two-dimensional (2D) numerical electrothermal simulation, the character of heating of SOS CMOS chip elements under the action of single voltage pulses was determined. The experiments carried out on SOS CMOS chips confirmed the validity of the developed numerical model of thin structure heating under the action of single voltage pulses. It was confirmed that the dependence of the pulse electric strength level on a single voltage pulses (SVP) length for SOS CMOS chips is weaker than that for CMOS chips fabricated using bulk or epitaxial technologies.
A uniform strategy is developed for testing discrete semiconductor devices and ICs for voltagesurge hardness, allowing comparison of differing models including ICs of high functional complexity. Performance specifications are defined, justified, and implemented for a voltage-surge simulator intended for electrical-overstress hardness tests of ICs. On this basis, a test bed is designed and built for evaluating the hardness of advanced ICs to voltage-surge effects, whether transient or permanent. A procedure is developed for predicting the electrical-overstress hardness of ICs, which enables one to detect both out-of-tolerance and functional failures during testing. The procedure and the test setup are validated by experiments with specific ICs.
