Wide-bandgap semiconductors offer substantial benefits for electronic devices operating at extreme conditions such as high temperature, high power, and high speed. Silicon Carbide (SiC) is attractive because of its high critical breakdown field, high thermal conductivity, and high electron saturation velocity. In addition to these important material characteristics, the high-quality thermal oxide on SiC enables metal–oxide–semiconductor field-effect transistors (MOSFETs) for power applications. This chapter discusses the effects of Nitrogen (N) on electron trapping at silicon dioxide (SiO2)/SiC interfaces as revealed by temperature-dependent, high-frequency C–V and transient capacitance spectroscopy techniques. Two different methods of introducing N at the SiO2/SiC interface were used: postoxidation Nitric Oxide (NO) annealing and ion implantation of N near the SiC surface prior to thermal oxidation. Although a detailed understanding of the mechanism of N passivation remains elusive, a reduction of the interface state density using the NO annealing process was the breakthrough that led to the recent commercialization of 4H-SiC power MOSFET circuits.

To investigate the mechanism by which Sb at the SiO2/SiC interface improves the channel mobility of 4H-SiC MOSFETs, 1 MHz capacitance measurements and constant capacitance deep level transient spectroscopy (CCDLTS) measurements were performed on Sb-implanted 4H-SiC MOS capacitors. The measurements reveal a significant concentration of Sb donors near the SiO2/SiC interface. Two Sb donor related CCDLTS peaks corresponding to shallow energy levels in SiC were observed close to the SiO2/SiC interface. Furthermore, CCDLTS measurements show that the same type of near-interface traps found in conventional dry oxide or NO-annealed capacitors are present in the Sb implanted samples. These are O1 traps, suggested to be carbon dimers substituted for O dimers in SiO2, and O2 traps, suggested to be interstitial Si in SiO2. However, electron trapping is reduced by a factor of ∼2 in Sb-implanted samples compared with samples with no Sb, primarily at energy levels within 0.2 eV of the SiC conduction band edge. This trap passivation effect is relatively small compared with the Sb-induced counter-doping effect on the MOSFET channel surface, which results in improved channel transport.

We report the use of hydrogen annealing to implement the substantial recovery of the a-face (1 1 (2) over bar 0) crystal structure and the 4H SiC MOSFET inversion layer mobility following material degradation by reactive ion etching (RIE). The results impact the processing of SiC trench MOSFETs where the a-face sidewall forms a significant portion of the conducting semiconductor channel. (C) 2014 Elsevier B.V. All rights reserved.

A numerical procedure to calculate the drain-current (ID) vs. gate-voltage (VG) characteristics from numerical solutions of the Poisson equation for organic Thin-Film Transistors (TFTs) is presented. Polaron transport is modeled as two-dimensional charge transport in a semiconductor having free-carrier density of states proportional to the density of molecules and traps with energy equal to the polaron-hopping barrier. The simulated ID-VG curves are proportional to the product of the density of free carriers, calculated as a function of VG, and the intrinsic mobility, assumed to be a constant independent of temperature. The presence of traps in the oxide was also taken into account in the model, which was applied to a TFT made with six monolayers of pentacene grown on an oxide substrate. The polaron-hopping barrier determines the temperature dependence of the simulated ID-VG curves, trapping in the oxide is responsible for current reduction at high bias and the slope of the characteristics near threshold is related to the metal-semiconductor work-function difference. The values of the model parameters yielding the best match between calculations and experiments are consistent with previous experimental results and theoretical predictions. Therefore, this model enables to extract both physical and technological properties of thin-film devices from the temperature-dependent dc characteristics.

Engineered or 'virtual' substrates are of interest to extend the range of epitaxially-grown semiconductor heterostructures available for device applications. To this end, elastically strain-relaxed square features up to 30 µm in size and having an in-plane lattice constant as much as 0.49% larger than the lattice constant of GaAs were fabricated from MOCVD-grown GaAs/In0.08Ga0.92As/GaAs heterostructures by the in-place bonding method, using either AlAs or Al0.7Ga0.3As as the sacrificial layer. TEM images show that the solution-bonded interface is flat with a network of sessile edge dislocations that accommodates the different in-plane lattice constants of the feature and the GaAs substrate and a small rotation of the bonded features. Micro-Raman spectroscopy, which has a spatial resolution of ∼1 µm, was shown to be useful for characterizing lattice mismatch strain ≥ 0.0023, i.e. with an order of magnitude lower sensitivity than high-resolution XRD.

The current vs. voltage (I-V) characteristics of single crystal rubrene Organic Field-Effect Transistors (OFETs) and polycrystalline poly(p-phenylenevinylene) (PPV) films are modeled using the polaron transport theory presented in a previous work [A. F. Basile et al., J. Appl. Phys. 115, 244505 (2014)]. The model is first applied to rubrene OFETs, where transport is two-dimensional and is confined near the interface between the insulator and the organic semiconductor. By considering the effect of image charges in the insulator and by assuming a constant intrinsic mobility, we reproduce both the positive and the negative temperature dependences of the channel mobilities measured on OFETs having a gate dielectric and an air-gap insulator, respectively. In addition, we adapt this model to the three-dimensional transport in PPV films, characterized by effective mobilities which depend on temperature, charge density, and electric field. We show that the I-V characteristics of these materials can be matched by the numerical solution of the Poisson and drift-diffusion equations assuming a constant intrinsic mobility. The polaron binding energy can account for the thermally activated behavior of the I-V characteristics and for the increase of the effective mobility at high applied voltages. Therefore, this model enables to extract the intrinsic transport parameters of organic semiconductors, independent of the device structure, and of the measurement conditions.

Capacitance-voltage (C-V) and Deep-Level-Transient Spectroscopy (DLTS) measurements were performed on Metal-Oxide-Semiconductor (MOS) capacitors fabricated on 4H-SiC with the SiO2 layer grown by Sodium-Enhanced Oxidation. This technique has yielded 4H-SiC MOS transistors with record channel mobility, although with poor bias stability. The effects of the mobile positive charge on the C-V characteristics and DLTS spectra were investigated by applying a sequence of positive and negative bias-temperature stresses, which drifted the sodium ions toward and away from the SiO2/4H-SiC interface, respectively. Analytical modeling of the C-V curves shows that the drift of sodium ions in the SiO2 layer during the voltage sweep can explain the temperature dependence of the C-V curves. The effects of lateral fluctuations of the surface potential (due to a non-uniform charge distribution) on the inversion layer mobility of MOS transistors are discussed within a two-dimensional percolation model. (C) 2014 AIP Publishing LLC.

Deep level defects in n-type GaAs1−xBix having 0 < x < 0.012 and GaAs grown by molecular beam epitaxy (MBE) at substrate temperatures between 300 and 400 °C have been investigated by Deep Level Capacitance Spectroscopy. Incorporating Bi suppresses the formation of an electron trap with activation energy 0.40 eV, thus reducing the total trap concentration in dilute GaAsBi layers by more than a factor of 20 compared to GaAs grown under the same conditions. We find that the dominant traps in dilute GaAsBi layers are defect complexes involving AsGa, as expected for MBE growth at these temperatures.

Low-temperature capacitance-voltage (C-V) characteristics of n-type In0.53Ga0.47As metal-oxide-semiconductor (MOS) capacitors, presented by Paterson et al. [J. Appl. Phys. 110, 114115 (2011)], are modeled by analytical and numerical calculations of the capacitance taking into account the slow response of neutral donors and interface traps to the measurement test signal. This model provides an explanation for the absence of the dip near flat band in the high frequency C-V characteristics, contrary to the prediction based on the ideal MOS capacitance. These calculations also show that a broad energy distribution of interface-traps can explain the broadening of the C-V curve.

A procedure to calculate capacitance-voltage (C-V) characteristics from numerical solutions of the Poisson equation for metal-oxide-semiconductor (MOS) capacitors with traps located both at the oxide/semiconductor interface and in the semiconductor is presented. This method is tested for the simple case of a uniform distribution of a single acceptor or donor level in the semiconductor, for which an approximate analytical solution was derived by analogy with the results obtained for a Schottky diode within the depletion approximation. This method is then applied to model the high-frequency C-V curves of n-type 4H- and 6H-SiC MOS capacitors, which show a kink at depletion bias voltages that broadens with decreasing temperature below 150 K. This feature of the high-frequency capacitance occurs at the same temperature and voltage range as a signal detected by constant capacitance deep-level-transient spectroscopy (CCDLTS) measurements and attributed to SiC traps. When only interface traps are considered, the trap energy distribution that is required to reproduce the kink in the C-V curves is not consistent with the trap energy distribution determined from CCDLTS measurements. Numerical simulations show that traps in the SiC epi-layer near the SiO2/SiC interface as well as interface traps with energies close to the SiC conduction band are necessary to explain both the CCDLTS measurement results and the temperature dependence of C–V curves.

Temperature dependent capacitance-voltage (C-V) and constant capacitance transient spectroscopy (CCDLTS) measurements have been performed to investigate the role of N in improving the transport properties of 4H-SiC MOS transistors. The higher channel mobility in the N pre-implanted transistors is due at least in part to activation of a small fraction of the implanted N near the SiO 2 /SiC interface as donors in SiC during oxidation, thus reducing the effects of interface trapping. In addition, the absence of oxidation-induced near-interface defects, which were observed in NO-annealed capacitors, may contribute to the improved mobility in N pre-implanted transistors.

Temperature dependent capacitance-voltage (C-V) and constant capacitance transient spectroscopy (CCDLTS) measurements have been performed to investigate the role of N in improving the transport properties of 4H-SiC MOS transistors. The higher channel mobility in the N pre-implanted transistors is due at least in part to activation of a small fraction of the implanted N near the SiO2/SiC interface as donors in SiC during oxidation, thus reducing the effects of interface trapping. In addition, the absence of oxidation-induced near-interface defects, which were observed in NO-annealed capacitors, may contribute to the improved mobility in N pre-implanted transistors.

The electrical properties of the SiO2/SiC interface fabricated by sodium-enhanced oxidation (SEO) of n-type 4H-SiC were studied by temperature-dependent C-V and constant-capacitance deep level transient spectroscopy (CCDLTS). With the exception of near-interface traps in the SiC epi-layer, which are not present in the SEO samples, the trap species observed in SEO capacitors are the same as those observed in both standard-oxidized and NO-annealed MOS capacitors. Total electron trapping in accumulation is comparable in SEO and NO-annealed capacitors; however, the traps in SEO capacitors are located at the interface whereas tunneling into oxide traps is observed in NO-annealed samples. A series of bias-temperature stress tests show that electron trapping is essentially unchanged when mobile sodium ions are moved toward the interface. The improved mobility attained by this process compared to NO annealing may be due to the absence of near-interface SiC traps in SEO samples.

Deep level transient spectroscopy (DLTS) measurements were performed on p-i-n diodes having i-regions that include a GaAs1-xBix layer sandwiched between two GaAs layers, all grown at T < 400 degrees C. A GaAs1 Bi-x(x)/GaAs heterostructure with Bi fraction x = 4.7% grown at 285 degrees C was found to have several traps in concentrations of similar to 5 x 10(15) cm(-3). The location of the observed traps in the i-region is determined from simulations of the band diagrams of these devices at the bias conditions used for the DLTS measurements and confirmed by DLTS spectra taken at various filling voltages.

Metal-oxide-semiconductor (MOS) interfaces on n-type 4H and 6H-SiC annealed in nitric oxide (NO) for various times were electrically characterized by high-frequency capacitance-voltage and deep-level-transient spectroscopy (DLTS) measurements. Different types of traps were distinguished by DLTS based on the energy-resolved DLTS spectra and comparing DLTS spectra from the two polytypes. Oxide traps, found at much higher densities in the larger bandgap 4H-SiC, are reduced by NO annealing, and their capture behavior is analytically modeled with a tunneling-dependent capture rate. An interface trap distribution is found in 6H-SiC MOS centered at 0.5 eV below the conduction band. Near interface traps in the SiC within 0.1 eV below the conduction band edge, detected at equal concentrations in both polytypes, are not passivated by NO annealing.

Incorporation of nitrogen (N) atoms by ion implantation prior to oxidation of SiO2/4H-SiC interfaces has been investigated by capacitance-voltage (C-V) characteristics and constant capacitance deep-level-transient spectroscopy (CCDLTS) measurements. The shift of the C-V curves to negative voltages can be explained by the partial activation of implanted N atoms during oxidation. The maximum amplitude of the CCDLTS spectra, proportional to the density of near-interface oxide traps, decreases with increasing N dose, but remains significantly larger than that of SiO2/SiC interfaces fabricated by post oxidation annealing in nitric oxide (NO). Intrinsic defects in the SiC epi-layer associated with implantation damage are also observed in N-implanted samples. In contrast, electron traps energetically close to the SiC conduction band, detected in NO annealed samples and presumably introduced during oxidation, are not observed in N-implanted samples. The improved transport characteristics of MOS transistors fabricated on N-implanted epi-layers compared to those fabricated by NO annealing is suggested to result from the effects of the greater N donor concentration and also possibly to the suppression of shallow electron traps in the SiC epilayer. (C) 2011 American Institute of Physics. [doi: 10.1063/1.3583574]