We evaluate the feasibility of several critical elements for the next generation high performance computing (HPC) Nanosheet (NS) technology. A simple NS pFET SiGe channel provides 40% mobility increase and 10% performance gain over a Si channel, with reduced threshold voltage (Vt) and improved negative bias temperature instability (NBTI). Both volumeless multi-Vt and metal multi-Vt, defined by ultra-thin nFET work function metal (nWFM), enhance the performance due to good Vt uniformity and improved reliability. We also demonstrate that the suspension (Tsus) can be reduced to 9nm for further device performance improvement.

A baseline TiAl-containing ALD electrode is established, with properties in line with reported workfunction (WF) materials for scaled RMG nFETs, values below 4.6eV requiring a 25Å layer. Furthermore, a novel ALD metal-compound material, MX, is shown to enable at least 10Å further scaling of the electrode stack due to its superior scavenging power. It can be finely tuned by the film thickness, allowing for a remarkable 20-30meV WF delta per ALD cycle over a minimum 600meV range. The wet etchability of the electrodes makes multi-Vt and dual-WF integration possible. MX does not degrade transfer characteristics and reliability of RMG FinFETs, while the thinner nWF electrode enables reduced gate resistance, as verified down to 20nm metal gate lengths. For the first time, taking advantage of the MX compound scavenging power to control oxygen filaments, we demonstrate an all-ALD HfO 2 -based ReRAM. Forming voltages match those achieved by optimized PVD contacts, while scaling the active electrode thickness by a factor of 4x, down to 5nm. Conformality of the layers enables vertical-ReRAM architectures with reduced line resistance. We conclude the developed electrode can facilitate both logic scaling beyond the 10nm node, and 3D memory technology.

2018 International Conference on Solid State Devices and Materials,In-situ Plasma Conditioning of InGaAs / High-κ Interface Layers for Defect Density Control Compatible with Scalable FinFET Integration

Channel thickness T CH dependence of electron mobility μ EFF in thin In 0.53 Ga 0.47 As channels was investigated at temperatures T from 35 to 300 K using conventional parametric and pulsed I D -measurements, including a novel technique with time resolution down to 10 ns. It is show that accurate mobility measurements can be obtained using low T and/or fast pulsed measurements, thus avoiding significant underestimations of μ EFF due to charge trapping with slow/parametric measurements. Furthermore, annealing is demonstrated to strongly suppress charge trapping, which results in μ EFF = 1015 cm 2 /Vs at T CH = 7.1 nm, carrier density N s = 3 × 10 12 cm -2 , and T = 300 K. We demonstrate that room-temperature μ EFF degrades by less than 10% as T CH is scaled from 300 nm down to 7 nm, thus indicating that there is no “mobility bottleneck” down to T CH = 7 nm.

We report the fabrication of short-channel FinFETs on InGaAs-on-silicon wafers using the aspect ratio trapping (ART) technique. We demonstrate excellent short-channel control down to 20 nm gate length due to scaled fin width down to 9 nm and reduction of parasitic bipolar effect (PBE). PBE that plagues III-V NFETs with gate-all-around (GAA) or III-V-on-insulator (III-V-OI) structures can be significantly suppressed by optimized ART FinFET technology. We demonstrate record high on-current ION and low drain leakage current for short gate lengths in the 20–32 nm range for InGaAs-on-silicon NFETs.

High-Ge-content (HGC) SiGe FinFETs in a “replacement High-K and metal-gate” (RMG) process flow and with aggressive EOT scaling are demonstrated, for the first time. HGC SiGe pMOS FinFETs with high-mobility, record-low RMG long-channel SS=66mV/dec and great short-channel characteristics down to L G =21nm have been demonstrated. Gate stack and transport properties down to sub-4nm fin widths (W FIN ) have been also studied for the first time. We demonstrate excellent RMG mobility and reliability at aggressive EOT~7Å, and excellent μ eff =220cm 2 /Vs at N inv =10 13 for fins with W FIN ~4nm, outperforming state-of-the-art devices at such dimensions and providing very promising results for FinFET scaling for future high-performance FinFET generations.

Self-aligned InGaAs channel MOSFET has been demonstrated on both InP and Si substrate using CMOS compatible device structure and process flow. Peak transconductance GMSAT over 2200 μS/μm has been achieved, at L EFF = 30 nm and supply voltage V DD = 0.5 V. These processes and devices are well-suited for future generations of high-performance CMOS applications at short gate lengths and tight gate pitches.

We demonstrate high-performance self-aligned In0.53Ga0.47As-channel MOSFETs with effective channel length L-EFF down to 20 nm, peak transconductance G(MSAT) over 2200 mu S/mu m at L-EFF = 30 nm and supply voltage V-DD = 0.5 V, thin inversion oxide thickness T-INV = 1.8 nm, and low series resistance R-EXT = 270 Omega.mu m. These MOSFETs operate within 20% of the ballistic limit for L-EFF <= 30 nm and are among the best In0.53Ga0.47As FETs in literature. We investigate the effects of channel/barrier doping on FET performance and show that increase in mobility beyond similar to 500 cm(2)/Vs has progressively smaller impact as L-EFF is scaled down. Our self-aligned MOSFETs were fabricated using a CMOS-compatible process flow that includes gate and spacer formation using RIE, source/drain extension (SDE) implantation, and in-situ-doped raised source/drain (RSD) epitaxy. This process flow is manufacturable and easily extendable to non-planar architectures.

Phosphorus passivation of the SiO2/4H-SiC interface lowers the interface trap density and increases the field effect mobility for n-channel MOSFETs to twice the value of 30-40cm(2)/V-s obtained using standard NO nitridation. Passivation using P2O5 introduced with an SiP2O7 planar diffusion source (PDS) converts the oxide layer to phosphosilicate glass (PSG) which is a polar material. BTS (bias-temperature-stress) measurements with MOS capacitors and FETs show that the benefits of reduced interface trap density and increased mobility are offset by unstable flat band and threshold voltages. This instability can be removed by etching away the PSG oxide and depositing a replacement SiO2 layer. However, trap densities for etched MOS capacitors are "NO-like" (i.e., higher), which would lead one to expect a lower mobility if MOSFETs are fabricated with the PSG / etch / deposited oxide process.

We describe experimental and theoretical studies to determine the effects of phosphorous as a passivating agent for the SiO2/4H-SiC interface. Annealing in a P2O5 ambient converts the SiO2 layer to PSG (phosphosilicate glass) which is known to be a polar material. Higher mobility (approximately twice the value of 30-40 cm(2)/V s obtained using nitrogen introduced with an anneal in nitric oxide) and lower threshold voltage are compatible with a lower interface defect density. Trap density, current-voltage and bias-temperature stress (BTS) measurements for MOS capacitors are also discussed. The BTS measurements point to the possibility of an unstable MOSFET threshold voltage caused by PSG polarization charge at the O-S interface. Theoretical considerations suggest that threefold carbon atoms at the interface can be passivated by phosphorous which leads to a lower interface trap density and a higher effective mobility for electrons in the channel. The roles of phosphorous in the passivation of correlated carbon dangling bonds, for SiC counter-doping, for interface band-tail state suppression, for Na-like impurity band formation and for substrate trap passivation are also discussed briefly. Published by Elsevier Ltd.

Metal-oxide-semiconductor (MOS) interfaces on n-type 4H and 6H-SiC annealed in nitric oxide (NO) for various times were electrically characterized by high-frequency capacitance-voltage and deep-level-transient spectroscopy (DLTS) measurements. Different types of traps were distinguished by DLTS based on the energy-resolved DLTS spectra and comparing DLTS spectra from the two polytypes. Oxide traps, found at much higher densities in the larger bandgap 4H-SiC, are reduced by NO annealing, and their capture behavior is analytically modeled with a tunneling-dependent capture rate. An interface trap distribution is found in 6H-SiC MOS centered at 0.5 eV below the conduction band. Near interface traps in the SiC within 0.1 eV below the conduction band edge, detected at equal concentrations in both polytypes, are not passivated by NO annealing.

The analysis of trapping phenomena in 4H- and 6H-SiC MOS capacitors from C-V and CCDLTS measurements is presented. Three categories of defect levels are distinguished: namely, oxide traps, semiconductor bulk traps, and interface states. NO annealing results in a dramatic decrease of the density of the interface states and the oxide traps in both polytypes, but does not reduce that of the SiC bulk traps.

The electrical properties of the SiC/SiO2 interface resulting from oxidation of the n-type 6H-SiC polytype were studied by hi-lo CV, temperature dependent CV and constant capacitance deep level transient spectroscopy (CCDLTS) techniques. Several trap species differing in energy and capture cross section were identified. A trap distribution at 0.5 eV below the 6H-SiC conduction band energy and a shallower density of states in both the 6H and 4H polytyes are passivated by post-oxidation NO annealing. However, other ultra-shallow and deeper defect distributions remain after nitridation. The latter may originate from semiconductor traps.

Several transport models are investigated in the context of two-dimensional fiber composites. We compare the thermal and electrical transport through the fiber composites as a function of the conductivity ratio and the fiber density. Three models will be considered and compared: 1) discretized solutions, 2) equivalent resistance, and 3) effective medium approximation. In the case of electrical transport, where the conductivity of the fiber is presumably many orders of magnitude larger than the matrix, the second model provides a fast and reliable way to predict conductance of the combined system. However, if the two materials are similar in conductivity, the second model fails to accurately capture the conductivity. Thermal transport is predicted using the discretized model because the conductivity ratio is non-negligible. The third model is an analytic approximation based on Maxwell’s equation and is used to predict both types of transport through a compound with inclusions of ellipsoidal geometry. The analytic model works well for lower conductivity ratios and all area densities but under-predicts conductivity for high-conductivity ratios.

In this paper, nitridation of thermally oxidized (0001) 4H-SiC will be discussed using nitrogen oxide and nitrogen plasma annealing. The interface trap density and channel mobility was reported as a function of interfacial nitrogen content by varying NO annealing time. Accurate elemental concentration was calculated using medium energy ion scattering spectroscopy and nitrogen incorporation in SiO 2 -SiC interface was presented and results were compared using other techniques such as SIMS.

The SiO2/SiC interface limits optimum SiC MOSFET performance due to a high density of interface states (D¿¿), which is reduced in devices that receive post-oxidation NO-annealing. Also, the interface state density in the 6H polytype is generally lower, approaching that of the NO treated 4H. In this work, interface states are investigated in both as-oxidized (AO) and NO-annealed (NO) MOS capacitors fabricated from n-type epitaxial (0001) 4Hand 6H-SiC. Oxidation was done in dry O2 at 1150°C followed by 30 min in Ar ambient. The NO exposure was at 1175°C for 2h. Constant capacitance deep level transient spectroscopy (CCDLTS) results are compared with the D¿¿ from hi-lo C-V and temperature dependent C-V measurements.

The total dose radiation response of nitrided and non-nitrided n-type 4H-SiC is reported for metal oxide semiconductor capacitors exposed to 10-keV X-rays under positive bias. The radiation response is affected strongly by differences in the SiC band gap and interface/near interface SiO2 trap density from typical Si MOS devices. Significantly higher net trapped positive charge densities were observed in nitrided n-SiC MOS capacitors compared to the non-nitrided samples. The mechanisms contributing to the differences in the charge trapping in these devices are discussed. Differences in the interfacial layer between SiO2/Si and SiO2/SiC are responsible for the observed dissimilarities in charge trapping behavior

Simultaneous measurements of the transmittance and the resistance were carried out on 20-nm-thick VO2 wires during the semiconductor-to-metal transition (SMT). They reveal an offset between the effective electrical and optical switching temperatures. This shift is due to current percolation through a network of nanometer-scale grains of different sizes undergoing a SMT at distinct temperatures. An effective-medium approximation can model this behavior and proves to be an indirect method to calculate the surface coverage of the films.