Memristive crossbar arrays are attractive for matrix-vector operations for AI algorithms deployed in IoT and edge applications due to their power efficiency. However, they are vulnerable to manufacturing process variations that are manifested as perturbations of the matrix coefficients, resulting in loss of performance. In this paper, we investigate how the performance of Hyperdimensional Computing (HDC) systems, an emerging AI paradigm, can be ensured in the presence of such variations. We investigate the benefits of multi-bit HDC, as opposed to binary, on limited-dimension (practical) crossbar arrays. A backpropagation based training method is developed next, that minimizes the impact of variability on classification accuracy. The training is quantization-aware and achieves variability-resilience without exceeding practical crossbar array size limitations. Further, a built-in testing and tuning algorithm is developed that uses compact tests and per-device digital fine-tuning of (low-rank) matrix transformations of the crossbar inputs and outputs. A novel tuning metric is used that enables the use of such compact tests. Simulations on 8-bit HDC demonstrate that variability-resilient training can improve yield up to 86.6% and testing combined with digital tuning on just 200 selected training data samples can further improve yield up to 96.8% on representative test datasets.

Transformer networks have achieved remarkable success in Natural Language Processing (NLP) and Computer Vision applications. However, the underlying large volumes of Transformer computations demand high reliability and resilience to soft errors in processor hardware. The objective of this research is to develop efficient techniques for design of error resilient Transformer architectures. To enable this, we first perform a soft error vulnerability analysis of every fully connected layers in Transformer computations. Based on this study, error detection and suppression modules are selectively introduced into datapaths to restore Transformer performance under anticipated error rate conditions. Memory access errors and neuron output errors are detected using checksums of linear Transformer computations. Correction consists of determining output neurons with out-of-range values and suppressing the same to zero. For a Transformer with nominal BLEU score of 52.7, such vulnerability guided selective error suppression can recover language translation performance from a BLEU score of 0 to 50.774 with as much as 0.001 probability of activation error, incurring negligible memory and computation overheads.

Binary Hyperdimensional Computing primitives offer significant energy and hardware benefits for power-constrained edge and portable AI applications, but are vulnerable to timing and soft errors in the associative memory storing high-dimensional representations, particularly under voltage overscaling, which causes significant accuracy loss. In this work, class hypervectors are represented in matrix form, with columns ordered by criticality with respect to classification accuracy and the critical columns clustered into submatrices via cosine similarity. Since traditional algorithmic checksums suffer from aliasing in binary representations, we use permutation-based checks on submatrix columns for error detection. For correction, we introduce a majority-vote column reconstruction (MVCR) algorithm: erroneous critical columns are replaced by a bit-wise majority vote across their submatrix, while erroneous non-critical columns are suppressed to zero. Validated on SRAM-based platforms under voltage scaling, the approach achieves up to 4× improvement in error resilience over state-of-the-art methods with minimal overhead.1

State-space models (SSMs) are widely used for sequence modeling, are attractive for their linear-time complexity as an alternative to attention mechanisms, but remain vulnerable to soft errors that corrupt hidden states and degrade inference. We propose a low-overhead error detection and correction framework that relies on a compact, quantized, and pruned redundant backup predictor network (BPN) to detect and correct errors in the internal SSM states, called hidden-states, at runtime. By comparing the dynamics of the primary and backup models, the method identifies abnormal behavior and selectively restores corrupted activations with minimal computational and memory cost. Experiments demonstrate that our approach preserves near- nominal accuracy.

Level set methods underpin modern safety techniques such as control barrier functions (CBFs), while also serving as implicit surface representations for geometric shapes via distance fields. Inspired by these two paradigms, we propose a unified framework where the implicit surface itself acts as a CBF. We leverage Gaussian process (GP) implicit surface (GPIS) to represent the safety boundaries, using safety samples derived from sensor measurements to condition the GP. The GP posterior mean defines the implicit safety surface (safety belief), while the posterior variance provides a robust safety margin. Although GPs have favorable properties such as uncertainty estimation and analytical tractability, they scale cubically with data. To alleviate this issue, we develop a sparse solution called sparse Gaussian CBFs. To the best of our knowledge, GPIS has not been explicitly used to synthesize CBFs. We validate the approach on collision avoidance tasks in two settings: a simulated 7-DOF manipulator operating around the Stanford bunny, and a quadrotor navigating in 3D around a physical chair. In both cases, Gaussian CBFs (with and without sparsity) enable safe interaction and collision-free execution of trajectories that would otherwise intersect the objects.

Generative adversarial networks (GANs) are promising for a range of applications, including image translation and denoising, as well as synthetic data generation. These applications can be mapped to memristive crossbar arrays (MCAs) for ultra-high energy efficiency and portability. However, conductance variation within analog crossbars degrades the quality of the GAN outputs and necessitates robust post-manufacturing testing. We propose a two-stage adaptive test framework for compute-in-memory (CiM) based GANs, comprising an exhaustive test and a compact test. The exhaustive test measures the inception score of a device under test (DUT) by applying a large number of noise vectors, called the exhaustive noise set. To reduce test time, a compact test estimates the inception score of a DUT from a carefully chosen subset of these vectors, called the compact noise set. The compact noise set is determined by a binary mask optimized with a novel backpropagation-guided algorithm to minimize the difference between the estimated and true inception scores of the DUTs. Finally, to leverage both the accuracy of the exhaustive test and the speed of the compact test, the proposed adaptive test framework first applies the compact test to every DUT. Only the DUTs that yield low confidence in classifications are then subjected to the exhaustive test. Experiments show that this adaptive approach achieves less than 1% test escapes while offering up to 7.26× speedup compared to exhaustive test.

The testing time of analog/mixed-signal (AMS) circuits limits the volume of tested parts that can be shipped to end customers and the utilization of automatic test equipment. Traditional test flows apply a fixed-size test stimulus to each device under test (DUT), leading to unnecessary test overhead. This paper presents CODA, a confidence-driven adaptive testing framework for AMS circuits that enables early test termination once sufficient confidence is reached regarding the quality (“good” vs. “bad”) of a tested device. CODA applies a piecewisecontinuous stimulus in short phases without interruption, with each phase consisting of a few time steps of device stimulation and data acquisition. Each phase is analyzed in order as soon as response data is available, using Gaussian mixture model (GMM)-based classifiers with adaptive test limits to enable early stopping for clearly “good” and “bad” devices (as determined by their design specifications). The test stimulus is optimized offline to improve as-early-as-possible “good” vs. “bad” discrimination with high confidence while maintaining high defect coverage. Clearly “good” or clearly “bad” devices are detected early, with marginal devices requiring larger test times (more test phases). Simulation results on mixed-signal circuits under realistic process variations and defects demonstrate a $2-4 \times$ reduction in average test time and better coverage compared to existing techniques. The proposed framework supports FPGA-based deployment with reduced-precision floating-point arithmetic, making it suitable for low-latency production test environments.

Modern wireless communications systems deploy massive MIMO systems with large numbers of transmit and receive antennas and analog-digital RF transceiver architectures that admit RF beamforming. These systems need to be tested and tuned postmanufacture to ensure signal quality. In analog architectures, this poses a problem due to the lack of observability of internal circuit nodes and due to the convergence of multiple RF beamforming chains into a combined baseband signal from which it is difficult to de-embed individual RF chain behaviors. Existing test techniques estimate nonlinearities in RF chains up to the third order and require significant frequency bandwidth to test multiple RF chains in a MIMO system in parallel, thereby reducing the overall test time. In this research, to improve testing efficiency, overlapping test tones over a minimal frequency range are applied to each of the MIMO RF chains in parallel, allowing specifications of individual RF chains up to fifth-order distortion to be determined accurately. For postmanufacture tuning, a response feature clustering approach followed by an implicit cost-driven tuning procedure is proposed. Tuning for error vector magnitude (EVM) and signal-to-interference ratio (SiNR) is performed under power constraints. Experimental results show that the proposed parallel testing methodology is 1.7x more frequency-efficient than existing techniques, and the proposed postmanufacture tuning algorithm can tune a receiver with four RF chains in 1.8 ms.

Stringent quality requirements for safety-critical applications drive the demand for "zero defects" in modern ICs. In this context, delay characterization of standard cells for resistive open defects is an increasing concern due to aggressive timing margins in digital circuits. The problem is made worse by the large number of open defect sites in standard cells, combined with a wide range of defect resistance values for each site. This incurs possible prohibitive costs for defect simulation and characterization. To alleviate this complexity, we propose Resistive Fault Dominance (RFD) for resistive open defects. RFD eliminates simulations of certain open defects with intermediate defect resistance values that are guaranteed to exceed specified timing margins for standard cells, based on tests for specific "dominant" open defects. This can significantly reduce the computational costs of cell library characterization and simulation effort by 84%-91%. An algorithmic fault simulation methodology for resistive open defects on parasitic-extracted (PEX) transistor-level netlist is developed.

Resistive Random-Access Memory (RRAM) crossbar array-based Deep Neural Networks (DNNs) are increasingly attractive for implementing ultra-low-power computing for AI. However, RRAM-based DNNs face inherent challenges from manufacturing process variability, which can compromise their performance (classification accuracy) and functional safety. One way to test these DNNs is to apply the exhaustive set of test images to each DNN to ascertain its performance; however, this is expensive and time-consuming. We propose a signature-based predictive testing (SiPT) in which a small subset of test images is applied to each DNN and the classification accuracy of the DNN is predicted directly from observations of the intermediate and final layer outputs of the network. This saves the test cost while allowing binning of RRAM-based DNNs for performance. To further improve the test efficiency of SiPT, we create the optimized compact set of test images, leveraging image filters and enhancements to synthesize images and develop a cascaded test structure, incorporating multiple sets of SiPT modules trained on compact test subsets of varying sizes. Through experimentation across diverse test cases, we demonstrate the viability of our SiPT framework under the RRAM process variations, showing test efficiency improvements up to 48X over testing with the exhaustive image dataset.

As autonomous vehicles edge closer to widespread adoption, enhancing road safety through collision avoidance and minimization of collateral damage becomes imperative. Vehicle-to-everything (V2X) technologies, which include vehicle-to-vehicle (V2V), vehicle-to-infrastructure (V2I), and vehicle-to-cloud (V2C), are being proposed as mechanisms to achieve this safety improvement. Simulation-based testing is crucial for early-stage evaluation of Connected Autonomous Vehicle (CAV) control systems, offering a safer and more cost-effective alternative to real-world tests. However, simulating large 3D environments with many complex single- and multi-vehicle sensors and controllers is computationally intensive. There is currently no evaluation framework that can effectively evaluate realistic scenarios involving large numbers of autonomous vehicles. We propose eCAV – an efficient, modular, and scalable evaluation platform to facilitate both functional validation of algorithmic approaches to increasing road safety, as well as performance prediction of algorithms of various V2X technologies, including a futuristic Vehicle-to-Edge control plane and correspondingly designed control algorithms. eCAV can model up to 256 vehicles running individual control algorithms without perception enabled, which is 8× more vehicles than what is possible with state-of-the-art alternatives.

Online deep reinforcement learning (deep RL)-based systems are being increasingly deployed in a variety of safety-critical applications. Due to the dynamic nature of the environments they work in, onboard reinforcement learning (RL) hardware is vulnerable to soft errors from radiation, thermal effects and electrical noise that corrupts the results of computations. Existing approaches to on-line error resilience in machine learning systems have relied on the availability of large training datasets to configure resilience parameters. This is not always feasible for online RL systems. Similarly, other approaches involving specialized hardware or modifications to training algorithms are difficult to implement for onboard RL applications. In contrast, we present a novel error resilience approach for online RL that leverages running statistics of neuron output values collected across the (real-time) RL training process to configure error detection thresholds (called checks) for the deep RL forward pass. Similarly, we formulate checks on the deep RL backward pass using running statistical thresholds on reduced-dimension checksums of online learning weight updates to rapidly detect and correct errors in online deep RL training. In this methodology, statistical concentration bounds leveraging running statistics are used to diagnose neuron outputs or weights as erroneous. The use of running statistics allows the checks to adapt to changes caused by continual on-line RL training. Erroneous neurons are set to zero (suppressed) in the forward pass. Erroneous weight updates are frozen, allowing nonerroneous weight updates to proceed and allowing online learning without rerunning training episodes. Our approach is compared against the state of the art and validated on several RL algorithms as well as a hardware validation platform.

Compute-in-memory (CiM) based convolutional neural network (CNN) accelerators achieve low-power inference, utilizing memristive crossbar arrays for matrix multiplications. However, inherent conductance variations within the crossbar introduce computational errors. These errors propagate to the CNN output and cause image misclassification, leading to substantial accuracy degradation. This paper addresses the critical challenge of efficient and reliable post-manufacture testing for CiM-based CNN accelerators. We propose a novel test image sampling methodology, which iteratively applies sampled images from the CNN's testing dataset using progressive random sampling (PRS) to a device under test (DUT) and estimates a confidence interval for the DUT accuracy. Based on the confidence interval and the acceptable accuracy threshold, the test labels a DUT as "pass" or "fail". Furthermore, if we have access to an initial set of DUTs, we apply the images from the CNN's testing dataset to these DUTs and leverage the DUT outputs to rank-order test images. We develop a sequential estimation test (SET) framework, where the images from the CNN's testing dataset are sequentially applied according to a predetermined rank and the test terminates when a DUT can be confidently labeled as "pass" or "fail" based on the applied images. In each case, the number of applied test images adapts to the quality of the DUT. Experiments show that PRS and SET achieve 2.2x and 4.6x speedup compared to state-of-the-art test methodologies.

The field of artificial intelligence (AI) has taken a tight hold on broad aspects of society, industry, business, and governance in ways that dictate the prosperity and might of the world's economies. The AI market size is projected to grow from $189 billion in 2023 to $4.8 trillion by 2033. Currently, AI is dominated by large language models (LLMs) that exhibit linguistic and visual intelligence. However, training these models requires a massive amount of data scraped from the web as well as large amounts of energy (50-60 GWh to train GPT-4). Despite these costs, these models often hallucinate, a characteristic that prevents them from being deployed in critical application domains. In contrast, the human brain consumes only 20W of power. What is needed is the next level of AI evolution in which lightweight domain-specific multimodal models, especially compact models with 10–20B parameters for bounded domains, with higher levels of intelligence can reason, plan, and make decisions in dynamic environments with real-time data and prior knowledge, while learning continuously and evolving in ways that enhance future decision-making capability. This will define the next wave of AI, progressing from today's large models, trained with vast amounts of data, to nimble energy-efficient domain-specific agents that can reason and think in a world full of uncertainty. To support such agents, hardware will need to be reimagined to allow system-level energy efficiencies ≥1000X over the state of the art for targeted domain tasks, subject to accuracy, latency, and coverage constraints. Such a vision of future AI systems is developed in this work.

While resistive random access memory (RRAM) based deep neural networks (DNN) are important for low-power inference in IoT and edge applications, they are vulnerable to the effects of manufacturing process variations that degrade their performance (classification accuracy). However, to test the same post-manufacture, the (image) dataset used to train the associated machine learning applications may not be available to the RRAM crossbar manufacturer for privacy reasons. As such, the performance of DNNs needs to be assessed with carefully crafted dataset-agnostic synthetic test images that expose anomalies in the crossbar manufacturing process to the maximum extent possible. In this work, we propose a dataset-agnostic post-manufacture testing framework for RRAM-based DNNs using Entropy Guided Image Synthesis (EGIS). We first create a synthetic image dataset such that the DNN outputs corresponding to the synthetic images minimize an entropy-based loss metric. Next, a small subset (consisting of 10-20 images) of the synthetic image dataset, called the compact image dataset, is created to expedite testing. The response of the device under test (DUT) to the compact image dataset is passed to a machine learning based outlier detector for pass/fail labeling of the DUT. It is seen that the test accuracy using such synthetic test images is very close to that of contemporary test methods.

Modern analog mixed-signal (AMS) devices manufactured in advanced CMOS processes pose significant testing and post-manufacture tuning challenges. Measurement of the specifications of AMS components is generally difficult as this requires the use of a range of dedicated tests while defect-based testing on the other hand, requires extensive defect simulations that are compute-intensive. To overcome these limitations, this research proposes OATT; a testing and post-manufacture tuning approach for AMS circuits that is designed to stress the performance of the device under test (DUT), formalize a statistical (multidimensional Gaussian) distribution of the expected response of known "good" devices (inliers), and use test limits grounded in theoretical statistics to classify all out-of-distribution devices (outliers) as "bad." It is an alternative test approach in that it does not explicitly target simulation of defect mechanisms. Tuning is performed to transform individual outlier DUT responses to those resembling inlier devices by modulating hardware tuning knobs, such as bias voltages and currents, using a reinforcement learning algorithm. Circuit simulations and hardware results demonstrate the viability and efficiency of the proposed approach.

Resistive random access Memory (RRAM) based spiking neural networks (SNN) are becoming increasingly attractive for pervasive energy-efficient classification tasks. However, such networks suffer from degradation of performance (as determined by classification accuracy) due to the effects of process variations on fabricated RRAM devices resulting in loss of manufacturing yield. To address such yield loss, a two-step approach is developed. First, an alternative test framework is used to predict the performance of fabricated RRAM based SNNs using the SNN response to a small subset of images from the test image dataset, called the SNN response signature (to minimize test cost). This diagnoses those SNNs that need to be performance-tuned for yield recovery. Next, SNN tuning is performed by modulating the spiking thresholds of the SNN neurons on a layer-by-layer basis using a trained regressor that maps the SNN response signature to the optimal spiking threshold values during tuning. The optimal spiking threshold values are determined by an off-line optimization algorithm. Experiments show that the proposed framework can reduce the number of out-of-spec SNN devices by up to 54% and improve yield by as much as 8.6%.

Resistive random access memory (RRAM) based memristive crossbar arrays enable low power and low latency inference for convolutional neural networks (CNNs), making them suitable for deployment in IoT and edge devices. However, RRAM cells within a crossbar suffer from conductance variations, making RRAM-based CNNs vulnerable to degradation of their classification accuracy. To address this, the classification accuracy of RRAM based CNN chips can be estimated using predictive tests, where a trained regressor predicts the accuracy of a CNN chip from the CNN's response to a compact test dataset. In this research, we present a framework for co-optimizing the pixels of the compact test dataset and the regressor. The novelty of the proposed approach lies in the ability to co-optimize individual image pixels, overcoming barriers posed by the computational complexity of optimizing the large numbers of pixels in an image using state-of-the-art techniques. The co-optimization problem is solved using a three step process: a greedy image down-selection followed by backpropagation driven image optimization and regressor fine-tuning. Experiments show that the proposed test approach reduces the CNN classification accuracy prediction error by 31% compared to the state of the art. It is seen that a compact test dataset with only 2-4 images is needed for testing, making the scheme suitable for built-in test applications.

Efficient and low-energy camera signal processing is critical for battery-supported sensing and surveillance applications. In this research, we develop a video object detection and tracking framework which adaptively down-samples frame pixels to minimize computation and memory costs, and thereby the energy consumed, while maintaining a high level of accuracy. Instead of always operating with the highest sen-sor pixel resolution (compute-intensive), video frame (pixel) content is down-sampled spatially, to adapt to changing camera environments (size of object tracked, peak-signal-to-noise-ratio (i.e, PSNR) of video frames). Object detection and tracking is supported by a novel video resolution-aware adaptive hyperdimensional computing framework. This leverages a low memory overhead non-linear hypervector encoding scheme specifically tailored for handling multiple degrees of resolution. Previous classification decisions of a moving object based on its tracking label are used to improve tracking robustness. Energy savings of up to 1.6 orders of magnitude and up to an order of magnitude compute speedup is obtained on a range of experiments performed on benchmark systems.

Resistive random access memory (RRAM) is highly attractive for use in deep neural networks (DNNs) due to its ability to perform matrix-vector multiplications with ultra-low power consumption, which is essential for implementing DNNs. However, testing and tuning RRAM-based DNNs is challenging due to the vulnerability of RRAM crossbars to manufacturing process variations. This difficulty is compounded by the complexity of modern DNNs and the large number of test stimuli (e.g., images) required to assess performance, such as classification accuracy. Post-manufacture tuning is further complicated by the need to test the DNN through each tuning iteration to ensure convergence to acceptable performance levels. This research proposes a machine learning-assisted alternative testing and tuning framework for DNNs that: (a) allows DNNs to be tested with a limited number of test stimuli (few test images) and (b) enables post-manufacture tuning of complex DNNs to be performed in tens of seconds, as opposed to hours or more. The core methodology, along with associated algorithms and test cases, is described.