A fast fluorescence lifetime imaging microscopy (FLIM) system using compress sensing and a single-pixel camera enables real-time imaging of biological dynamics. Dual detection paths provide high-speed (20 fps) or multispectral measurements, enhancing biomedical analysis. (c) 2025 The Author(s)

The development of an electronic readout platform specifically designed for real-time range verification systems to be used in hadrontherapy is presented. Such modular systems are composed of multiple 64-channel gamma camera modules based on pixelated LYSO scintillator coupled with 15 mu m cell SiPM arrays. Both the detector and the associated electronics are specifically designed to support range verification through Prompt Gamma Imaging (PGI). Such an application requires a specific electronics readout able to operate in a wide energy range (up to 10 MeV) and at high counting rates (up to 1 Mcps/ch). The system's modular structure allows it to accommodate various treatment plans and overcomes limitations related to patient anatomy and beam positioning. The detector is composed of 64-channel modules, each covering an area of 52.6 x 52.6 mm2, with each module consisting of two 32-channel front-end electronics readout and data acquisition systems (DAQ). The SiPMs outputs are processed by two 16-channel SITH ASICs. These integrated circuits are optimized for reading SiPM arrays and can handle high input currents (on the order of tens of milliamps), which makes them suitable for large-area photodetectors and high energy gamma rays. The DAQ architecture is based on a 32-channel sub-module and consists of two multi-channel Analog to Digital Converters (ADC) and an FPGA. The energy signals from the ASICs are digitized by an octal-channel, 12-bit, 65 Msps ADC. This ADC is multiplexed 2:1 to read all 16 channels of each ASIC. For precise timing measurements, 32 Time-to-Digital Converters (TDCs) are integrated within the FPGA, achieving a temporal resolution better than 300 ps (FWHM). In FPGA firmware a time-coincidence strategy has been implemented in order to reconstruct interactions resulting from Compton scattering and pair production.

Time-resolved ultrafast phenomena with hard X-ray radiation are key research areas for applications like pump-and-probe spectroscopy. The demand for higher performance drives advancements in detector technologies and multichannel acquisition techniques. This motivates our proposal for an innovative fully digital 3D (x-y-time) imager for hard X-rays. Key challenges in detector design include improving time resolution, spatial resolution (limited by the multipixel approach), and quantum efficiency, which is low for silicon detectors in the hard X-ray range. We propose using a Separate Absorption and Multiplication Avalanche PhotoDiode (SAM-APD) based on III-V semiconductors. GaAs-based alloys, with higher atomic number and mobility, offer significantly better efficiency and speed for hard X-ray absorption compared to silicon. Regarding acquisition systems, the shift towards multichannel methods and the need to minimize power and area per channel has led to the transition from traditional pixelated voltage-mode electronics to time-based acquisition systems, where both spatial (x and y) and timing information are linked to the detection event's time. By coupling a large-area GaAs SAM-APD (several mm in diameter) to two Cross Delay Lines (CDLs) and a 4 -channel 15 -ps precision FPGA-based Time-to-Digital Converter (TDC), we aim to achieve temporal and spatial resolutions of tens of picoseconds and hundreds of micrometers. This approach offers a powerful alternative to pixelated systems, requiring neither aggressive lithography nor one readout channel per pixel, using only four channels.

Fluorescence microscopy is nowadays one of the most diffused techniques to study photophysical processes and molecular interactions in both biomedical and material science fields. Since each fluorophore is characterized by a specific emission spectrum and lifetime, it is essential not only to spatially localize its position but also to measure its spectral and temporal properties with a multispectral fluorescence lifetime imaging microscope (λFLIM). Moreover, to study rapidly evolving samples, a measurement system capable of fast acquisitions is needed. λFLIM systems are currently limited on acquisition speed and cannot reach high throughput. In this work, we propose a novel wide-field multispectral fluorescence lifetime imaging microscope based on a 16-channel silicon photomultiplier (SiPM) array. Our system, thanks to the SiPM technology along with the single pixel camera and compress sensing approaches is able to acquire multidimensional measurements (space, spectrum, and time) at high frame rate. We validate the system on moving fluorescent samples capturing snapshots at a frame rate of up to 13 fps. The developed system could enable enhanced specificity in real-time fluorescence imaging in biological and biosensing applications.

Time-to-Digital Converters (TDCs) are increasingly vital in modern measurement systems, with Field-Programmable Gate Arrays (FPGAs) offering a cost-effective platform despite challenges in asynchronous circuit design. Among various solutions, Tapped Delay-Line (TDL)-TDCs stand out for balancing precision, speed, and resource efficiency. However, a primary concern in FPGA-based TDL-TDCs are the Bubble Errors (BEs), i.e., spurious zeros introduced in the information code in the TDL that put the measurement precision at severe risk. The main goal of this contribution is to investigate the distribution of BEs, utilizing the Clock Region Crossing (CRC) within the FPGA as a case study, in order to demonstrate theoretically and experimentally that if BEs are manipulated properly, they create an interpolation effect that reduces the quantization error of the TDL-TDC. The analysis is carried out on a 256-tap fully integrated TDL-TDC implemented in a 28 nm Xilinx Artix 100T FPGA. The outcome confirms the potential to use CRC-BEs instead of suppressing them with precision increasing up to 0.17 ps r.m.s., or by almost 2% while also supporting the correctness of the model.

Time-resolved spectroscopic and electron–ion coincidence techniques are essential to study dynamic processes in materials or chemical compounds. For this type of analysis, it is necessary to have detectors capable of providing, in addition to image-related information, the time of arrival for each individual detected particle (“x, y, time”). The electronics capable of handling such sensors must meet requirements achievable only with time-to-digital converters (TDC) with a resolution on the order of tens of picoseconds and the use of a field-programmable gate array (FPGA) to manage data acquisition and transmission. This study introduces the design and implementation of an innovative TDC based on two FPGAs working symbiotically with different tasks: the first (AMD/Xilinx Artix® 7) directly implements a TDC, aiming for a temporal precision of 12 picoseconds, while the second (Intel Cyclone® 10) manages the acquisition and connectivity with the external world. The TDC has been optimized to operate on eight channels (+ sync) simultaneously but is potentially extendable to a greater number of channels, making it particularly suitable for coincidence measurements where it is necessary to temporally correlate multiple pieces of information from various measurement systems.

Multi-channel data management is crucial in a world where big data processing is extensively used in research and business. Histogramming is a common technique employed to detect, analyze, and store enormous volumes of data in real-time, making it useful for industrial applications in fields such as biology, chemistry, medical imaging, and spectroscopy. Due for them programming simplicity and low-cost large amount of memory, general-purpose temporal computing processors are commonly used, but they lack the ability to perform parallel computation at high-performance. Field-Programmable Gate Array (FPGA) is a powerful parallel computing solution proposed by both the scientific and industrial worlds, but it is equipped with little memory for these applications. Thus, a hybrid spatial/temporal computing histogram generator has been proposed, which uses a low-area multi-channel histogramming engine in programmable logic which is expanded thanks to an external Double Data Rate Synchronous Dynamic Random Access Memory (DDR) driven by a MicroBlaze Soft Processor Core. The proposed system has been validated on a Xilinx 28-nm 7-Series Artix-7 XC7A100T FPGA hosted on a Nexys4 Evaluation Board. Thanks to this hybrid solution, up to 128 channels can handle in a low-end FPGA occupies 207 LUTs and 325 flip-flops per channel plus a total 630 kb of total BRAM shared between all channels; a power consumption of 10.1 mW per channel is measured.

We present the development of the Data Acquisition System (DAQ) of a modular detector for dose monitoring in hadrontherapy based on pixelated LYSO scintillator coupled with 15 μm cell SiPM arrays. The detector and electronics are specifically designed for Prompt Gamma Imaging (PGI) in hadrontherapy applications. The modularity allows the system to be used in a variety of treatment plans, not being strictly limited by the physical constraints of the patient and beam position. The camera is organized in 64-channel module of 55×55 mm 2 area, each composed of two 32-channel front-end electronics system. Two 16 channel SITH ASIC are used to acquire the SiPMs current signals. This ICs are specifically designed for the readout of arrays of SiPMs and are able to process high input currents (tens of mA range) in order to be used with large-area photodetectors and high-energy gamma rays. The DAQ is based on two Analog Front-End circuits (AFE) and a FPGA for each 32-channel module. The ASICs energy outputs are converted by an octal-channel, 12-bit, 65 Msps ADC multiplexed 2:1 to read all the 16-channel of the ASIC. 32 Time-to-Digital Converters (TDCs) are implemented in a single FPGA to obtain the timing information with a precision better then 300ps (FWHM). Acquiring hit position, energy, and timestamp for each event is crucial for implementing time coincidence strategies that help to accurately reconstruct events, especially those involving Compton scattering and pair production, which are the dominant interaction mechanisms for high-energy gamma rays in PGI. We present preliminary experimental measurements acquired with two 16 and 32-channel prototypes obtaining a 511 keV energy resolution around 12% FWHM and a CRT of 200ps (FWHM) with 3×3 mm 2 SiPMs coupled with 3×3×5 mm 3 LYSO scintillators.

Over the last ten years, the need for high-resolution time-domain digital signal production has grown exponentially. More than ever, applications call for a digital-to-time converter (DTC) that is extremely accurate and precise. Skew compensation and camera shutter operation represent just a few examples of such applications. The advantages of adopting a flexible and rapid time-to-market strategy focused on fast prototyping using programmable logic devices—such as field-programmable gate arrays (FPGAs) and system-on-chip (SoC)—have become increasingly evident. These benefits outweigh those of performance-focused yet expensive application-specific integrated circuits (ASICs). Despite the availability of various architectures, the high non-recurring engineering (NRE) costs make them unsuitable for low-volume production, especially in research or prototyping environments. To address this trend, we introduce an innovative DTC IP-Core with a resolution, also known as least significant bit (LSB), of 52 ps, compatible with all Xilinx 7-Series FPGAs and SoCs. Measurements have been performed on a low-end Artix-7 XC7A100TFTG256-2, guaranteeing a jitter lower than 50 ps r.m.s. and offering a high dynamic range up to 56 ms. With resource utilization below 1% and a dynamic power dissipation of 285 mW for our target FPGA, the design maintains excellent differential and integral nonlinearity errors (DNL/INL) of 1.19 LSB and 1.56 LSB, respectively.

Within the Data Acquisition (DAQ) system of the 1 Mpixel camera based on DEPFET Sensor with Signal Compression (DSSC) at the European X rays-Free Electron Laser (EuXFEL), the DEPFETs are read-out by two Field-Programmable Gate Array (FPGA) stages: the Input Output Board (IOB), which currently houses an End-of-Life (EoL) low-area and low-power Xilinx 45-nm 6-Series Spartan-6 (i.e., XC6LX45T), and the Patch Panel Transceiver (PPT) with an high-performance Xilinx 28-nm 7-Series Kintex-7 device. The IOB is the first acquisition stage located near the detector, housed within a vacuum-sealed metallic container, and operates at low temperature (i.e., -20°C). This specific working environment imposes significant constraints on the physical size of the board and compliance with thermal and current budgets. At EuXFEL a new detector development program is in the definition phase. This paper reports feasibility studies performed on the IOB, in order to provide, on one side spare parts for the existing installed detectors, and on the other, to check which kind of system could be compatible also for future operation. It is necessary to begin with a redesign of the IOB because the Spartan-6 FPGA it hosts is at End-of- Life (EOL). Moreover, using newer and more advanced FPGAs makes it natural to introduce features that can be compatible with future upgrades of the detectors at the European XFEL; e.g., higher pixel count, self-trimming, and pre-calibration. In this regard, two different models of Xilinx FPGAs at 16 nm, the SU65P Spartan UltraScale+ and the AU15P Artix UltraScale+, compatible with the current Spartan-6 in terms of package size, number of I/Os, amount of logic, and availability of transceivers, have been selected. This preliminary analysis covers aspects related to the estimation of resource usage, power consumption, operating frequency, and bandwidth, considering the current Spartan-6 FPGA and its firmware as reference.

With countless applications, time measurements are among industrial electronics' current most important challenges. This is not a matter of precision, which by now standard architectures have brought in the order of picoseconds and therefore at the physical limits of most common detection systems, but to the number of channels in continuous enormous growth. Just think about time-of-flight (TOF)-based applications like 3-D-imaging, time-of-arrival real-time locating systems, TOF positron emission tomography, and so on. This addresses the research on the design of new time-to-digital converters characterized by a huge number of channels and precision compliant with detectors' time resolution. In this context, field programmable gate array architectures provide fully digital and completely programmable solutions meeting the demands for flexible setups and speedy prototyping. The innovative contribution provided by the new counter architecture proposed consists of the reduction of the area required for implementation (only 110 SLICEs), with a consequent increase in the number of channels (up to hundreds in a tiny Aritx-7), much higher than the state-of-the-art multiphase solutions available today and of the new complete generation of the time estimates in real time, all while maintaining a state-of-the-art low power consumption and high resolution (up to 150 ps) and precision (up to 68.4 ps r.m.s.).

Modern applications require the ability to measure time events with high resolution, a full-scale range, and multiple input channels. Time-to-Digital Converters (TDCs) are a popular option to convert time intervals into timestamps. To reduce the time-to-market and Non-Recurring Engineering (NRE) costs, a Field-Programmable Gate Array (FPGA) implementation has been chosen. The high number of requested bits and channels, however, gives rise to routing congestion issues when routed in a parallel manner. In this paper, we will propose and analyze a novel solution, the Belt-Bus (BB), which involves a parallel-to-serial conversion of the timestamp stream coming from the TDC while maintaining chronological order and a sufficient high rate, and flagging the presence of timestamp overflow. Moreover, two new useful features are added. The first is a “Virtual Delay” to compensate for offsets due to cable length and FPGA routing path mismatch. The second is a “Virtual Dead-Time” to filter out unforeseen events. Finally, the BB was tested on a Xilinx 28 nm 7-Series Kintex-7 325T FPGA, achieving an overall data rate of 199.9 Msps with very limited resource usage (i.e., lower than a total of 4.5%), consuming only 480 mW in a 16-channel implementation.

This study investigated implementation strategies to optimize the precision of Tapped Delay Line (TDL) Time-to-Digital Converters (TDCs) designed for Xilinx 20 nm UltraScale Field-Programmable Gate Arrays (FPGAs). This optimization process aims to bridge the performance gap between FPGA-based TDCs, which are more flexible and suitable for fast prototyping, and the better-performing Application-Specific Integrated Circuit (ASIC) solutions, making FPGA-based TDCs viable for cutting-edge applications. Our key areas of focus included the optimal design of the decoder, the degree of sub-interpolation, and the placement of TDLs, with particular emphasis on the clocking distribution scheme within the Configurable Logic Block (CLB) to minimize the effects of Bubble Errors (BEs) and quantization error. The research led to the development and comparison of multiple TDL TDC solutions implemented on a Kintex UltraScale device (i.e., XCKU040-2FFVA1156E) housed on a KCU105 general-purpose Evaluation Board (EVB). From these, two main solutions emerged: one with high precision and one with low area. The first one was characterized by a Single-Shot Precision (SSP) of 2.64 ps r.m.s., and by Differential and Integral Non-Linearity (DNL/INL) Errors of 0.523 ps and 16.939 ps, respectively, occupying 883 CLBs and 126 kb of Block RAM (BRAM). The second one had an SSP of 3.75 ps r.m.s., a DNL of 0.599 ps, and an INL of 7.151 ps, and it occupies only 259 CLBs and 72 kb of BRAM.

The increasing accessibility of cutting-edge photon sources, such as the latest generation of FreeElectron Lasers (FELs) and synchrotron facilities, has substantially broadened research horizons, particularly in the investigation of chemical and physical dynamics like time-of-fligth mass spectrometry. Consequently, there is a need for a new generation of precise and flexible timeresolved acquisition systems. Two-dimensional particle detectors play a crucial role in this paradigm shift, evolving from mere pixelated imaging sensors to time-based devices capable of encoding the spatial coordinates of detected events into time delays, in addition to associating temporal information with each received event. In this sense, Cross Delay-Lines (CDLs) detectors play crucial roles. In addition to the information provided by the CDL, which can be obtained with a simple acquisition system based on 4-channel Time-to-Digital Converter (TDC), it becomes increasingly necessary to provide auxiliary measurement channels in order to acquire additional information to correlate with the CDL data. The acquisition electronics of these setups rely on TDCs based on Application-Specific Integrated Circuits (ASICs), followed by Field Programmable Gate Arrays (FPGAs) for data processing. However, the lack of adaptability and flexibility inherent in ASICs prompted us to explore a fully FPGA-based approach aimed at achieving outstanding precision at high measurement rate retaining the unparalleled flexibility that only an FPGA can offer. In the following work, we propose a system based on a 16-channel TDC with a precision of 12 ps r.m.s., 5 ns of dead-time, and 4 ps of integral non-linearity. In this regard, 4 channels of the TDC are connected to a CDL, achieving a spatial resolution up to $30 / 40 \ \mu \mathrm{m}$ FWHM, while the remaining 12 channels are used for detecting auxiliary events to be correlated with the spatial information.

Calibration of models and data structures is recurring in a large number of cross-cutting applications from finance to engineering. Even though there are numerous and well-established specific calibration techniques for each application sector, using Neural Networks (NNs) can improve performance. For instance, Tapped Delay-Line Time-to-Digital Converters (TDL-TDCs) implemented in Field Programmable Gate Arrays (FPGAs) are increasingly being used in a variety of research applications, such in the time-resolved spectroscopy or in medical imaging mainly for their high-precision and flexibility. Specific decoding on the sampled information from the TDL, together with calibration to compensate for non-idealities, (i.e., Bubble Errors, BEs, and Process–Voltage–Temperature fluctuations, PVTs) are carried out for generating the conversion of digital codes to time units. In this fundamental process, the impact of Machine Learning (ML) usage has not yet been investigated. In this paper, focusing on advanced FPGA devices (i.e., 28-nm, 20-nm, and 16-nm), we propose an approach based on NNs running in Python on a standalone PC to identify the optimal conversion from digital codes to timestamps, comparing it with the classical fully FPGA-based solution c literature. The experimental validations are performed on Artix-7 (XC7A100TFG256-2) and Kintex UltraScale (XCKU040-FFVA1156-2-E) in 28-nm and 20-nm technology nodes, achieving precision of 12.9 ps r.m.s. and 4.85 ps r.m.s., respectively. These results are in line with the state-of-the-art, demonstrating that in 28-nm technology, the bubble compression algorithm is sufficient to achieve high-precision, while reordering mechanism is crucial to compensate for BEs within the 16/20-nm technology node.

Recent developments in nuclear electronics have resulted in significant progress in time interval measurements. Detectors can now achieve timing performance in the order of tens of ps, requiring Time-to-Digital Converters (TDCs) that provide not only high-precision matching the detector’s jitter but also a large number of channels for parallel data acquisition. Designers are increasingly turning to fully-digital solutions, such as Field-Programmable Gate Arrays (FPGAs), due to its ability to offer flexibility in measurement setup and fast-prototyping. Proper discrimination of the analog signal output from detectors is crucial for accurately acquiring temporal information. The most suitable circuit for this task is the tunable Threshold Comparator (TC), due to its compactness. Various TC circuits can be found in the literature, whose threshold is generated using a Digital-to-Amplitude Converter (DAC) and the discrimination is performed by a ultra-fast comparator guaranteeing a jitter lower than few ps. However, in this solution the presence of the DAC significantly increases the circuit’s area occupancy, while the use of an ultra-fast comparator can dramatically increase power dissipation (up to tens of mW per channel). In this paper, we propose a fully FPGA-based architecture for a TC and TDC, targeting Xilinx 28-nm 7-Series FPGAs. Our design eliminates the need for an external comparator and replaces the DAC with a compact external Low-Pass Filter (LPF); additionally, we employ a Pulse-Width Modulator (PWM) implemented in firmware to achieve the desired threshold level. The proposed approach leads to a noteworthy reduction in power consumption (tens of mW) and hardware resources, while providing a comparable jitter performance worsen only by a factor 5 with respect a classical state-of-the-art TC circuit. Finally, the presented TC is interfaced with a compact multi-channels (up to 103) TDC with hundreds of picoseconds resolution (up to 156 ps) in a Axtix-7.

The European X-ray Free Electron Laser (EuXFEL) is a light source of the 4th generation which provides spatially coherent ultrashort X-ray pulses at high rate. The facility enabled unprecedented advancement in fundamental research, but also needed new detectors to fit the EuXFEL requirements, such as single photon resolution, large dynamic range, and high repetition rate: three 2D megapixel detectors have been developed to cope with the demanding environment. The DEPleted Field Effect Transistors (DEPFET) Sensor with Signal Compression (DSSC) detector is one of them. The parallel readout from each pixel is performed employing a dedicated Application Specific Integrated Circuit (ASIC). The generated data flow is read through a 2-stage Field Programmable Gate Array (FPGA)-based Data AcQuisition (DAQ) chain: the Input Output Board (IOB) controls the primary readout from 16 ASICs and serializes data on high-speed links that are sent to the Patch Panel Transceiver (PPT). It is also responsible for the clock distribution and timing control of the front-end and switched power channels. The PPT reorders and forwards the received data toward the EuXFEL back-end, and allows remote control over the whole DAQ. A first DSSC camera, based on miniaturized silicon drift detectors (mini-SDD) has been available for users’ experiments since 2019, and a second DEPFET-based camera is under construction. The IOB firmware has been thoroughly reviewed and modified to cope with the new DEPFET sensors’ physics and to improve the performance of both the mini-SDD and DEPFET versions. We present an overview of the DSSC, focusing on the DAQ, highlighting the main properties of the environment where the detector operates. We assess the firmware improvements introduced, with a particular focus on the IOB, and present the results obtained in comparison to the original firmware.

Modern applications like nuclear measurements, and energy discriminating detectors, to name a few of the most prevalent, have all witnessed a significant increase in timing measurements. For this purpose, high-performance Time-to-Digital Converters (TDCs) play an increasingly key role. However, in many setups, the measurement of occurrence time of an event is accompanied by the measurement of the energy associated with it. Therefore, the ideal would be to combine the measurements of the two parameters with the performance required by the specific experimental context. In literature, entirely time-based solutions are available, such as the Time-over-Threshold (ToT) technique, or mixed solutions in which the TDC, used for timing only, is coupled with a voltage-mode analog circuit for energy readout (a.k.a., amplitude of the signal), such as a PeakDetector (PD) or an integrator (INT) that interfaces via Analog-to-Digital Converter (ADC) to a digital system. This paper investigates the performance obtained in terms of energy (i.e., amplitude) and timing measurements, highlighting the strengths and weaknesses of the proposed approaches. Moreover, to minimize the impact of jitter, the ToT technique will also be validated using a Charge Readout (CR) circuit. The circuits were implemented on a Printed Circuit Board (PCB) and interfaced to a Xilinx 28-nm Artix-7 200T Field Programmable Gate Arrays (FPGA) housed in a Nexys Video. In the FPGA, in addition to the logic for interfacing with the ADC for amplitude read-out, a TDC with a precision of 12 ps r.m.s. is also included. The TDC is responsible not only for generating the timestamp for the PD and INT circuits but also for estimating the energy in the ToT with and without the CF. It can be observed that it is possible to detect amplitudes up to some volts with a precision of a few millivolts using both time-based and voltagemode approaches at rates of tens of Msps maintaining a temporal resolution of tens of picoseconds.

Many modern applications in various scientific, industrial, and consumer sectors, such as Time-of-Flight Positron Emission Tomography and 3D imaging scanning in medicine, or Particle Identification in nuclear physics, require the measurement of time intervals with both high-precision (picoseconds) and extremely large number of channels (hundreds). Among the most established Time Interval Meters (TIMs), Time-to-Digital Converters (TDCs) are increasingly a very popular choice, especially thanks to their extremely high flexibility, in the version implemented in Field Programmable Gate Array (FPGA) devices. However, the number of channels is becoming so high in the most advanced applications, that a single FPGA device is not sufficient to host the necessary architecture and therefore the problem arises of realizing a multi-FPGA based TDCs, necessarily all perfectly synchronized with each other. Given the picoseconds-precision required, the problem of TDCs synchronization is a very significant issue that requires the development of methodologies and techniques designed and developed ad hoc. The proposed solution is a structure that meets these needs and is implemented using a "main board" that hosts a 16-nm Xilinx Zynq UltraScale+ XCZU9EG-2FFVB1156 Multi-Processor System-on-Chip (MPSoC). The main board coordinates up to 8 FPGA-based "satellite boards", each hosting a Xilinx 28-nm 7-Series Kintex-7 XC7K410T-2FFG676I FPGA, in which a 16-channel, 12-picoseconds precision FPGA-based TDC is implemented. In this way, it is possible to manage up to 128 channels with a precision of 12 ps r.m.s. The satellite boards are connected to the main board via the Aurora protocol on Gigabit Transceiver Hardmacro (GTH), making it possible to achieve a data collection rate of 250 Msps by the main board. The entire system is housed in a 4U, 460 x 305 mm, 4U rack.

Optimum filters are granted increasing recognition as valuable tools for parametric estimation in many scientific and technical fields. The DPLMS method, introduced some twenty years ago, is especially effective among the synthesis algorithms since it derives the optimum filters directly from the experimentally acquired signal and noise waveforms. Two new extensions of the DPLMS method are here presented. The first one speeds up the synthesis phase and improves the energy estimation results by synthesizing optimum filters with automatically designed flat-top length. The second one improves the quality of parameter estimation in multi-channel systems by taking advantage of the inter-channel noise correlation properties. In this paper, the theoretical and functional aspects behind the DPLMS method for optimum filter synthesis are first recalled and illustrated in more detail. The two new DPLMS extensions are subsequently briefly introduced from the theoretical viewpoint and more thoroughly considered from the applicative perspective. The DPLMS optimum filters have been applied first to simulated signals with various amounts and characteristics of superimposed noise and then to the experimental waveforms acquired from a solid-state Ge detector. The results obtained are considered from both the absolute viewpoint and in comparison with those of more traditional, suboptimal filters. The obtained results demonstrate the effectiveness of the two new DPLMS extensions. For single-channel energy estimations, the synthesized optimum filters provide comparatively better results than the other tested filters. The DPLMS multi-channel optimum filters further enhance the quality of the estimations, compared to single-channel optimum filters, with non-negligible inter-channel noise correlation. The effectiveness and robustness of the DPLMS method in synthesizing high-quality filters for energy estimation will be tested soon within leading-edge multi-channel physics experiments.