In this work, we propose a hardware implementation architecture for ordered reliability direct error pattern testing (ORDEPT), a recently introduced decoding method for high-rate short linear codes. While ORDEPT necessitates a smaller number of test queries compared to the ordered reliability bits guessing random additive noise decoding (ORBGRAND) counterpart, testing of a query in ORDEPT includes an extra pattern completion operation. The proposed hardware implementation architecture adopts a pipelined scheduling strategy to achieve fixed throughput and latency. To reduce power, we propose early termination mechanisms based on the maximum number of candidate codewords and likelihood thresholding. Implemented in 65-nm CMOS technology, the proposed architecture demonstrates that ORDEPT and its thresholded variant achieve significantly lower latency and smaller area occupancy compared to ORBGRAND with the same decoding performance. For the Bose–Chaudhuri–Hocquenghem (BCH) $(128,113)$ code at a target frame error rate of $10^{-5}$ the proposed thresholded ORDEPT implementation achieves a latency of 81.9 ns, up to 67 times higher area efficiency and, up to 68 times lower energy per bit, compared to the ORBGRAND implementation.
Emerging edge intelligence applications require computing platforms that provide high-throughput inference and high energy efficiency under stringent power and resource constraints. Neuromorphic processors are promising candidates for such workloads due to their sparsity-aware and multiplication-free synaptic operations. However, existing neuromorphic processors often suffer from constrained throughput caused by global-barrier time-step scheduling and limited parallelism of fanout operations. This paper presents Fovea, a high-throughput single-core neuromorphic processor featuring a step-relay architecture supported by an efficient step-relay unit, allowing overlapped step execution across layers. An address-invariant row-aligned mapping scheme is further proposed enabling up to 1024-way parallel fanout operations across all layers. Additionally, a four-stage pipeline is introduced for fanout operations within each layer, achieving up to 1024 SOPs per cycle. Post-layout evaluation shows a peak throughput of 173.21 GSOPS and a minimum energy per SOP of 7.11 pJ/SOP. The peak-throughput operating point achieves an area efficiency of 9.25 GSOPS/mm2. Fovea provides $13.53\times $ higher throughput than SOTA single-core neuromorphic processors, while maintaining competitive area efficiency despite being implemented in an older 130 nm technology. After normalization to 40 nm technology, Fovea could achieve $35.06\times $ higher throughput and $13.68\times $ higher area efficiency with only 68.39% lower energy efficiency.
This paper proposes a new fixed-correlation based threshold driven simultaneous orthogonal matching pursuit (FT-SOMP) algorithm for wideband spectrum sensing that is implementation friendly, suitable for real-world scenario and delivers reliable detection performance. It achieves detection probabilities of 0.8 to 0.9 above -3 dB of signal-to-noise ratio (SNR). Subsequently, an matrix inversion-free technique has been suggested to reduce both hardware cost and reconstruction time of the wideband spectrum sensor (WSS) design based on the suggested FT-SOMP algorithm. In addition to aforementioned implementation-impacts of FT-SOMP algorithm, this work incorporated systolic-inspired resource sharing and efficient memory-accessing techniques to develop a highly hardware-efficient WSS architecture for our FT-SOMP algorithm, spanning from system- to micro-architecture-level designs. Furthermore, the proposed WSS architecture is implemented on an AMD Zynq-UltraScale+ MPSoC ZCU104 FPGA-board where it utilizes nominal hardware resources of 38171 LUTs, 19062 registers, 53 DSP-cores, 6.5 BRAM-tiles, and operates at a maximum clock frequency of 178.8 MHz with a total power consumption of 0.954W with short reconstruction time of $13.73~\mu $ s. Compared with the relevant and the state-of-the-art implementations, the proposed WSS achieves $4.62\times $ and $1.94\times $ higher hardware efficiencies, respectively. Finally, the hardware prototype of the proposed WSS is functionally validated using a digitally-emulated radio-frequency (RF) front-end and data-acquisition test-setup, under different spectrum-occupancy scenarios while sensing the FR3 band of prospective 6G cellular technology.
This paper analyzes frequency errors caused by mismatches in two-point modulation (TPM) for Frequency-Modulated Continuous-Wave (FMCW) chirp generation. The mismatches arise from VCO gain nonlinearity and process, voltage, and temperature (PVT) variations. We derive closed-form analytical expressions for frequency errors due to static mismatch, including start and end turn-around point (TAP) errors, charge pump pulses, and divider-step ripples, and dynamic mismatch, where the VCO gain varies during the chirp. For each case, closed-form formulas for the root-mean-square frequency error and the linearity parameter $Lin$ are provided in terms of chirp parameters and PLL specifications. This analysis offers insight into how each mismatch mechanism affects chirp linearity, enabling designers to predict performance degradation. All theoretical results are validated through behavioral simulations.
This work presents PADCIM, a 40-nm probabilistic approximate dynamic-logic based digital computing-in-memory (CIM) macro for energy-efficient CNN and Transformer acceleration. It has three key features: 1) Probabilistic approximate adder tree (PAAT) that balances approximation errors to suppress slope deviation and achieve low RMSE. 2) Full dynamic-logic computing circuits (FDCC) that combine NP-Domino cascading, compensation transistors, and a delay clock chain to reduce chip power, area, and delay. 3) XOR-based multi-bit computation scheme (XMCS) with bias error compensation to support accurate binary and multi-bit computations without extra encoder or look-up table circuits. Fabricated in 40-nm CMOS, PADCIM achieves a peak energy efficiency of 1966.9 TOPS/W and an average RMSE of 2.09% in the 1b/1b mode. Compared with the state-of-the-art approximate digital CIM, PADCIM reduces RMSE by $1.93\times $ while maintaining competitive energy efficiency. In the 4b/1b mode, it achieves 244.21 TOPS/W at 25% input toggle rate. System-level evaluations with hardware-consistent approximate network modeling show that PADCIM achieves 87.56% accuracy on CIFAR-10 with ResNet-14 and 82.42% accuracy on ImageNet-1K with ViT-B, demonstrating its effectiveness for both CNN and Transformer workloads.
