Nanoelectronics has the potential, and is indeed expected, to revolutionize information technology by the use of the impressive characteristics of nanodevices such as carbon nanotube transistors, molecular diodes and transistors, etc. A great effort is being put into creating an introductory course in nanotechnology. However, practically all courses focus on the physics, chemistry, and materials science aspects of this discipline. On the other hand, a more abstract, design-oriented introduction is desirable for electrical and computer engineering majors. In order to teach design-oriented nanotechnology, the teaching curriculum must be extended to include new concepts. In particular, it is necessary to supply the design principles, device models, and software simulation tools. This article describes our approach for introducing nanotechnology system design into the Electrical and Computer Engineering undergraduate curriculum at Stony Brook University. The approach consists of developing a nanodevice library for SPICE-like simulator and a 3-week module on nanotechnology system design utilizing this library. The module will be woven into an existing course on Integrated Electronics.

A compact modeling methodology for the skin effect in conductors with rectangular cross section is presented. Possible equivalent circuit topologies are reviewed, and their calibration on numerical simulation is discussed, highlighting the shortcomings of conventional calibration procedures. A new approach, based on the direct fitting of the impedance transfer function to numerical simulations, is shown to offer excellent accuracy for a wide range of cross-sectional wire aspect ratios. The new formulation also obviates the need for separating the wire internal and external inductances which is a prerequisite for all published models. Finally, a practical implementation of the model as an RL parallel network is presented.

We present a complete modeling technique for inductive parasitics, based on the vector potential equivalent circuit (VPEC) topology. Novel algorithms for layout extraction and sparsification are introduced. Examples are discussed in terms of CPU time, accuracy, and model complexity. Finally, extensions for high frequency applications are presented, including models for skin effect and full wave simulation.

Accounting for the effects of inductive, resistive as well as capacitive parasitics of interconnects and on-chip inductors is essential to the success of parasitic-aware RF circuit synthesis at high frequencies. This paper presents an approach for RF circuit synthesis, based on fast procedural layout generation and extraction of all parasitics using multiple extractors. While the parasitic capacitances are obtained using standard rule-based techniques, parasitic resistances and inductances are computed using a fast, yet accurate quasi-static inductance extraction method. Both self and mutual inductances and resistances of inductors and interconnects, which play a significant role at high frequencies, are accounted in the process. A simulated-annealing based optimization algorithm controls design space exploration. Synthesis results show that the proposed methodology yields designs that are more realistic and accurate compared to approaches that ignore resistive and inductive parasitics of interconnects.

We present a layout-in-loop synthesis method for radio-frequency LNAs, which uses symbolic performance models (SPMs), parameterized layout generator and high-frequency extraction techniques in the synthesis loop. The primary focus of this work is on performance estimation using efficient SPMs and development of techniques to include layout parasitics symbolically into the SPMs before the start of synthesis. SPMs for noise figure and distortion parameters are obtained using repetitive and weakly nonlinear symbolic analysis and are stored as pre-compiled element coefficient diagrams (ECDs). Speedy layout generation is achieved by using parameterized procedural layout generators and full parasitic extraction is done by using multiple extractors. Quasi-static extraction is used to obtain the critical parasitic effects of interconnects and on-chip inductors. The proposed methodology is used for the synthesis of low noise amplifiers (LNAs).

We present a compact topology for inductive parasitics, using the vector potential as a state variable. The model is local, i.e., only coupling between neighboring wires is explicitly modeled. However, the topology accounts for long-range coupling by propagating the vector potential from one wire to the next. Examples of rule-based generation and model reduction are presented for a digital bus.

A novel circuit topology for inductive coupling between interconnecting wires is presented. The model is local, i.e., only coupling between neighboring wires is explicitly modeled. However, the topology accounts for long-range coupling by propagating the vector potential from one wire to the next. Examples of model calibration, both directly from layout and as model-order reduction of a given inductance matrix, are presented for simple wiring structures.

An accurate and efficient simulation methodology for Si/sub 1-x/Ge/sub x/ HBTs is presented. A two-dimensional (2-D) drift-diffusion solver is employed for dc and ac characteristics, and one-dimensional (1-D) full-band Monte Carlo for transport in the base-collector high-electric-field region. Extrinsic parasitics are introduced as lumped circuit elements whose values are obtained from measurements and layout considerations. This approach not only reduces the computational cost of the simulation, but it also helps to differentiate the relevance of the intrinsic and extrinsic device parameters. We discuss the calibration of the simulation on a 0.25 /spl mu/m process and use a 1-D regional analysis in the quasi-static approximation to identify the major source of delay. Results of the delay analysis were used to improve device performance for the 0.16 /spl mu/m technology node.

We present three-dimensional heat-transport simulation for bipolar transistors. The simulations are validated on experimental data, and are employed to develop analytical models for the thermal resistance of devices fabricated on bulk and SOI substrate, and with deep-trench isolation. The cross-heating effect in multifinger devices is also modeled.

We review a recently proposed methodology for automatic generation of equivalent circuits from physical device simulation. The method is based on the calibration on a simplified equivalent-circuit model on simulation results, and can achieve an optimum balance of model complexity, accuracy, and generality. We discuss some of the possible applications of the technique to the modeling of active devices, parasitic elements, and complex physical effects such as selfheating and hot-carrier transport.

Analytical expressions for the thermal resistance of bipolar transistors on bulk and SOI substrates are presented. The models are derived on the basis of intuitive physical pictures and validated by comparison with experimental data and three-dimensional (3-D) device simulation. The effect of bulk and SOI substrates, shallow- and deep-trench isolation, and multiple emitter fingers is accounted for. All models are suitable for both hand calculations and computer-aided design.

We describe a low fabrication cost, high-performance implementation of SiGe BiCMOS on SOL The use of high-energy implant allows the simultaneous formation of the subcollector and an additional n-type region below the buried oxide. The combination of buried oxide layer and floating n-type region underneath results in a very low collector-to-substrate capacitance. We also show that this process option achieves a much lower thermal resistance than using SOI with deep trench isolation, both reducing cost and curbing self-heating effects.

In this work we investigate the effect of quantization at the polysilicon/oxide interface on the properties of n- and p-MOS transistors. As a consequence of the potential energy barrier, a dark space depleted of free carriers is created at the interface, which is slightly dependent on the applied bias. Both polysilicon capacitance and voltage drop in all regions of operation of modern MOS devices are dominated by quantum effects. Polysilicon quantization leads to a reduction in the gate capacitance in the same way as substrate quantization, and to a negative voltage shift, which is opposed to conventional substrate quantization. These effects are discussed in detail for dual-gate MOSFET's with ultra-thin oxides.

Measurements and Monte Carlo simulations of impact ionization in the base-collector region of SiGe HBTs are presented. A device with low germanium concentration (graded from 0 to 12%) is considered and no differences are found between the experimental multiplication factor in that device and the corresponding silicon control. Because impact ionization (II) occurs inside the bulk-Si collector, phonon and II scattering rates for bulk silicon can be used in the Monte Carlo simulation, avoiding the need to model the strained SiGe layers. Full-Band Monte Carlo simulations are shown to reproduce the multiplication factors measured in SiGe devices featuring different collector profiles.

Accurate simulations of advanced Si1-x Ge-x heterojunction bipolar transistors involve a range of different problems, whose solution demands different numerical approaches. In our simulation methodology, the complexity of each numerical method matches that of the problem at hand. We employ a 2D drift-diffusion solver for dc and ac characteristics, ID full-band Monte Carlo for transport in the base-collector high electric field region, and a 3D heat-transport solver for device selfheating. Extrinsic parasitics are introduced as lumped circuit elements whose values are obtained from measurements. This approach not only reduces the computational cost of the simulation, but it also helps to differentiate the relevance of the intrinsic and extrinsic device parameters. Such information can then be used for device optimization and for guidance in generating compact models.

We present a characterization of self-heating in a 0.25mum SiGe BiCMOS technology on bulk and SOI substrates. Measurements are compared with analytical models and simulations. Thermal coupling between emitter fingers and effect of metallization are also analyzed.

This letter describes an improved formula for the extraction of the polysilicon doping from the C-V characteristic of MOS transistors. Analytical approximations are presented for the inversion layer contribution, which was neglected in previous work. The new approach returns an estimate error smaller than 10% when the full substrate and poly quantization are accounted for. Practical application to experimental data is also addressed.

An inverse modeling technique for doping profile extraction from MOS C-V measurements is presented. The method exploits the "kink" effect observed near flat bands in low-temperature C-V curves to accurately estimate the dopant concentration at the oxide-silicon surface. The inverse modeling approach, based on a self-consistent Schrodinger-Poisson solver, overcomes the limitations of previous analytical methods. The accuracy of the doping extraction is demonstrated by successfully reconstructing doping profiles from simulated C-V curves, including abrupt variations of doping in the vicinity of the oxide interface. When applied to experimental data from boron- and phosphorus-doped samples, the technique is shown to provide a substantial improvement in resolution with respect to room-temperature C-V measurements.

We present a characterization of self-heating in a 0.25 /spl mu/m SiGe BiCMOS technology on bulk and SOI substrates. Measurements are compared with analytical models and simulations. Thermal coupling between emitter fingers and effect of metallization are also analyzed.

A two-dimensional MOS device simulator including quantum-mechanical enacts has been developed and applied to surface-and buried-channel p-MOS devices. The Schrodinger equation is solved retaining a large number of eigenstates, which are then used to build a modified classical distribution accounting for the high energy part of the distribution. With this approach, discontinuities in the gate capacitance near flat bands have been eliminated without introducing any empirical parameter. For accurate device simulation, experimental data on the hole mobility were collected, and a non-local mobility model was used for carriers in the bound levels. A standard mobility model is adopted instead for the classically-distributed carriers. Results are presented for the gate capacitance and drain current of 0.35 mum devices, showing a good agreement over a wide range of channel doping concentrations.