This study compares the scalability of charge-trap metal-oxide-semiconductor field-effect transistors (CT-MOSFETs) and charge-trap tunnel field-effect transistors (CT-TFETs) for high-accuracy analog vector-matrix-multiplication (VMM) operations for the first time. Featuring stronger gate-controllability, CT-TFETs demonstrate better channel length modulation ( $\lambda \text {)}$ and analog weight level difference ratio ( $\Delta {I}_{\text {W}}$ / ${I}_{\text {W{0}}}\text {)}$ than those of CT-MOSFETs in both long and short gate length ( ${L}_{\text {G}}\text {)}$ cases (500 and 65 nm), maintaining low VMM error in the scaled case. Consequently, CT-TFETs show ~6.25× higher tolerable IR drop range and 11-% higher MNIST classification accuracy than CT-MOSFETs in the 65-nm ${L}_{\text {G}}$ case.
Event-based vision sensors convert light intensity variations into asynchronous spike signals, featuring high temporal resolution and low data redundancy. However, event-driven detection technology is rarely applied to solar-blind ultraviolet (UV) detection. In this work, we demonstrate a 254 nm solar-blind UV event sensor based on $\beta $ -Ga2O3, which combines photodetectors with dual-channel complementary event-processing circuits. The device generates dual-polarity spike outputs whose amplitudes positively correlate with incident irradiance, with an event response time below 7.5 ms. A bias of 10 V yields an optimal analog threshold of 2.33 mW/cm2, balancing noise suppression and detection sensitivity without additional external filters. Array-level simulations based on experimental parameters verify reliable edge detection and motion tracking under dynamic gesture scenarios. This work proves the great potential of $\beta $ -Ga2O3 for neuromorphic solar-blind UV sensing, and offers a feasible solution for high-speed dynamic UV monitoring.
In this study, we present a novel simulation framework for negative capacitance field-effect transistors (NCFETs), rigorously incorporating position- and gate-bias-dependent partial polarization behavior in ferroelectric (FE) layers. While previous theoretical approaches primarily assumed fully polarized FE (FPFE) states, our method integrates Poisson’s equation, the nonequilibrium Green’s function (NEGF) formalism, and a minor loop FE polarization model to accurately simulate partially polarized FE (PPFE) states, which occur frequently under realistic operating conditions. Our results demonstrate that NCFETs operating under PPFE states demonstrate worsened subthreshold swing (SS) and drain-induced barrier lowering (DIBL) compared to the FPFE case. Specifically, we reveal that FPFE assumptions tend to overestimate the steepness of the switching behavior and illustrate how the magnitude of polarization distinctly affects the gate control and spatial conduction band profile. We further investigate and compare the impact of FE thickness and channel length on DIBL in FPFE- and PPFE-NCFETs, offering critical insights for the optimization of FE-based ultralow-power electronics.
A phenomenological mathematical (PM) model is proposed to describe the current–voltage ( $I$ – $V$ ) characteristics of silicon (Si) p-n junction diodes, based on a self-feedback mechanism. The self-feedback principle assumes that the rate of change of a physical quantity depends only on the quantity itself, i.e., $\text {d} {y}/\text {d} {x}={f}({y})$ . Experimental $I$ – $V$ measurements are performed under both forward and reverse bias conditions. In the forward bias region, the carrier concentration growth rate $\text {d} {n}/\text {d} {V}$ is modeled as proportional to ${n}+{n}_{{0}}$ , where ${n}+{n}_{{0}}$ denotes the background carrier concentration, accounting for diffusion dominated current transport. In the reverse-bias regime, the $I$ – $V$ behavior is divided into three distinct stages governed by different carrier dynamics: 1) Stage I: $\text {d} {n}/\text {d} {V} \propto {n}_{{1}-{n}}$ , where ${n}_{{1}}$ represents the saturation carrier concentration, reflecting minority carrier diffusion; 2) Stage II: $\text {d} {n}/\text {d} {V} \propto {n}$ , corresponding to avalanche multiplication; and 3) Stage III: $\text {d} {n}/\text {d} {V} \propto {n}_{{1}}+\delta $ , with $\delta \gt {0}$ as an empirical constant, capturing the effects of band-to-band tunneling and the steeper-than-avalanche rise in carrier concentration. Analytical expressions derived from the PM model exhibit excellent agreement with experimental data across the entire I–V curve. In contrast to conventional models that rely on idealized assumptions-such as constant carrier mobility or abrupt junction approximation-the proposed PM model captures the nonlinear evolution of carrier concentration through a self-feedback framework, enabling a unified description of both forward and reverse $I$ – $V$ characteristics. This work provides new insights into the mechanisms underlying charge transport in semiconductor diodes.
A silicon-on-insulator (SOI) power device with a self-charge-balanced low-resistance conductive layer (S-LC) is proposed and experimentally demonstrated in this article. A self-charge-balance of S-LC is established between the additional surface positively ionized donors and the negative MIS-coupled charges, thereby eliminating the dependence on additional n-type doping relative to p-type doping. The S-LC eliminates the inevitable current-path reduction and premature inner breakdown in conventional low-resistance conductive layers based on p-n junctions. The additional n-type doping region, requiring no extra mask or lithography process, serves as a low-resistance conductive layer, thereby reducing the specific on-resistance ${R}_{\text {on,sp}}$ . Consequently, a normalized conduction factor $\eta _{\text {C}}$ , which is consistently greater than one, is attained while maintaining a high breakdown voltage ${V}_{\text {B}}$ . In experiments, the S-LC introduced an additional n-type doping dose of $1\times 10^{{12}}$ ${\mathrm {cm}}^{-{2}}$ . Then, a measured low ${R}_{\text {on,sp}}$ of 4.7m $\Omega {\,}\cdot $ cm2 was observed in the S-LC device under a ${V}_{\text {B}}$ of 290 V, realizing a high figure of merit $\textit {FOM} = {V}_{\text {B}}^{{2}}$ / ${R}_{\text {on,sp}}$ of 17.89 MW/cm2 and a reduction of 70.5% when compared with the theoretical value of the triple RESURF technology under the same ${V}_{\text {B}}$ . Moreover, the S-LC lateral double-diffused MOSFET (LDMOS) has successfully passed a series of reliability tests, including high-temperature reverse-bias (HTRBs) and high-temperature gate-bias (HTGBs) tests.
Sub-10 nm nanoelectronics scaling demands channel materials combining superior electrostatic control, high mobility, and low power consumption. Tungsten diselenide ( ${\mathrm{WSe}}_{{2}}\text {)}$ has emerged as a premier 2-D candidate due to its tunable bandgap, atomic thickness, and ambipolar transport. This review systematically examines recent WSe2 field-effect transistor advancements across five core domains: architectures, doping, contact engineering, reliability, and applications. Advanced configurations, including dual-gate FETs, vertically stacked complementary FETs (CFETs), and steep-slope variants, significantly enhance scalability and energy efficiency. Surface charge transfer (SCT) and substitutional doping enable stable unipolar operation while preserving gate control. Contact optimization via van der Waals (vdW) interfaces and alloyed electrodes effectively mitigate Fermi-level pinning (FLP) and reduces contact resistance ( ${\mathrm{R}}_{\text {C}}\text {)}$ . Interfacial passivation with h-BN and plasma treatments robustly suppresses charge trapping and threshold voltage hysteresis. Finally, WSe2-FETs are positioned for transformative roles in low-power CMOS, flexible electronics, biosensors, neuromorphic computing, and optoelectronics, alongside key commercialization pathways.
