Motion estimation (ME) is one of the most time-consuming parts in video encoding system, and significantly affects the output quality of an encoded sequence. In this paper, we present hardware implementation of the Large Diamond Parallel search algorithm. This hardware is designed to be used as part of a complete H.264 video coding system. This architecture is simulated and tested using VHDL and synthesized using Altera Quartus II version 5.1. Also, This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The VHDL code is verified to work at 100 MHz in ALTERA Stratix II FPGA.

Block matching motion estimation algorithms have been developed for very different applications in image processing. In recent years, the variable block-size (VBS) motion estimation has been widely employed to improve the performance of the block matching algorithm. In this paper, we compare the performance of several variable block-size motion estimation algorithms based on merge and split procedures, and we propose a new algorithm based on the zoom effect. Many experiments results validate our procedure and illustrate the advantages and performance of our proposed algorithm compared to others. Our algorithm will be denoted here and after as: Zoom Motion Estimation (ZME).

Motion estimation in video coding standards, such as H.264/AVC, is considered to be the most timeconsuming encoding module. Motion estimation is generally performed on a 16x16 block, although in H.264/AVC, 7 different block sizes (16x16, 16x8, 8x16, 8x8, 8x4, 4x8 and 4x4) are allowed. The aim of this paper is to optimise the implementation of the motion estimation algorithm on the Texas Instruments’ TMS320C64 DSP. Specifically, the goal is to use the C64 set of instructions in order to optimise the Sum of Absolute Differences (SAD) engine within the motion estimation and to take advantage of the Direct Memory Access (DMA) to reduce the cycle cost in loading data from external to internal memory. Standard Assembly (SA) is used to implement the different SAD functions in order to exploit the C64 internal architecture and resources efficiently. Experimental results shows more than 75% improvement in terms of cycle cost compared to C code for each function.

In motion estimation, the search patterns with different shape and size have a large consequence on the searching speed and quality of performance. A popular example is the full search (FS) algorithm. Nevertheless, the high computational complexity of the FS algorithm has motivated several faster search strategies. However, the FS allows a better quality. In this paper, we compare the performance of several motion estimation algorithms for H.264/AVC video coding such as the three-step search (TSS), diamond search (DS), small diamond search (SDS), cross diamond search (CDS), hexagon-based search (HEXBS), nearest-neighbors search (NNS), and we propose a new one called Horizontal Diamond Search (HDS). Simulations show that HDS is particularly faster and more accurate in some kinds of sequences. This algorithm is especially suitable for videoconferencing applications.

In this paper, we study the computational complexity of the intra prediction module for video coding software according to H.264/AVC standard. We analyze separately the complexity of each intra mode for the implementation on TMS320C64 platform. The intra prediction unit consists of predicting the block's pixels from their neighbors according to different directional modes (horizontal, vertical, ...) and others non-directional (DC, planar). For each mode, we compute the number of the executional sub-units (add, shift, load, store...). Together with the number of necessary cycles to execute every instruction and the functional units that can perform these instructions, we can deduce the complexity of every intra mode. To estimate the total complexity of the intra prediction process, we assume that the encoder tests all intra modes. The total cycle's account is estimated by multiplying the number of cycles of each mode by the number of blocks in the picture. Our results indicate that our methodology for the complexity analyses of the intra prediction unit of the H.264/AVC provides a good approximation with respect to the experimental results.

In MPEG and VCEG standards, motion estimation is used to eliminate the temporal redundancy. Given that the motion estimation stage is very complex in terms of computational effort, a hardware implementation on a reconfigurable circuit is crucial for the requirements of different real time multimedia applications. In this paper, we present the design of a motion estimation circuit and its hardware implementation on FPGA based on "full search block matching" algorithm according to H.263 standard. We specified, simulated, and synthesized SAD's engine with VHDL description. The proposed design is implemented on a "stratix" FPGA using EPIS10B672C6 component. Our simulations confirm the functionality of the algorithm using "ModelSim" simulator and synthesis using the "Quartus" software provided by ALTERA. This study represents a mean stone for FPGA implementation of motion estimation algorithms.

With the increasing usage of multimedia technologies, image compression requires higher performances as well as new features. To address these needs in the specific area of continuous tone still image encoding, a new standard is currently being developed, the JPEG2000. It is not only intended to provide rate-distortion and subjective image quality performance superior to existing standards, but also to provide new features and functionalities that current standards can either not address them efficiently or in many cases cannot address them at all. Copyright (C) 2004 AEI.